added a bunch of files to allow sst1/cvg build out-of-the-box
This commit is contained in:
dborca
138
swlibs/fxmisc/ddglobal.h
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138
swlibs/fxmisc/ddglobal.h
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/*
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* ddglobal.h placeholder for Glide3x (SST1, SST96, CVG)
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*
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* Copyright (c) 2004 - Daniel Borca
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* Email : dborca@users.sourceforge.net
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* Web : http://www.geocities.com/dborca
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*/
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#ifndef DDGLOBAL_H_included
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#define ddgetenv(A) getenv(A)
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#define ddatoi(A) atoi(A)
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#define ddftol(A) ((long)(A))
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#define dd_itof_inv(A) (1.0f/(float)(A))
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#define ddatof(A) atof(A)
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#define ddpow(A, B) pow(A, B)
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#define ddsscanf(A, B, C) sscanf(A, B, C)
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/*
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* Perhaps this file should be personalized for each ASIC,
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* and then moved into the respective glide3x branches...
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*/
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#ifndef __CVGINFO_H__
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#if defined(SST1) || defined(SST96_FIFO)
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#include <sst1vid.h>
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#else /* !SST1 && !SST96_FIFO */
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// Video timing data structure
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typedef struct {
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FxU32 hSyncOn;
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FxU32 hSyncOff;
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FxU32 vSyncOn;
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FxU32 vSyncOff;
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FxU32 hBackPorch;
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FxU32 vBackPorch;
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FxU32 xDimension;
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FxU32 yDimension;
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FxU32 refreshRate;
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FxU32 miscCtrl;
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FxU32 memOffset;
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FxU32 tilesInX;
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FxU32 vFifoThreshold;
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FxBool video16BPPIsOK;
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FxBool video24BPPIsOK;
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float clkFreq16bpp;
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float clkFreq24bpp;
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} sst1VideoTimingStruct;
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/* Init code client callbacks to allow the init code to use the client
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* command fifo management code to do writes etc.
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*/
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typedef void (*FxSet32Proc)(volatile FxU32* const addr, const FxU32 val);
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/*
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** CVG Device Information Structure
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**
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*/
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// Initialization and configuration data structure
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typedef struct {
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FxU32 size; // size of this structure
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SstRegs *virtAddr[2]; // virtual memory base address
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FxU32 physAddr[2]; // physical memory base address
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FxU32 deviceNumber; // PCI device number
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FxU32 vendorID; // PCI vendor ID
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FxU32 deviceID; // PCI device ID
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FxU32 fbiRevision; // FBI revision number
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FxU32 fbiFab; // FBI Fab ID
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FxU32 fbiBoardID; // FBI board ID (poweron strapping bits)
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FxU32 fbiVideo16BPP; // FBI video display mode
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FxU32 fbiVideoWidth; // FBI video display X-resolution
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FxU32 fbiVideoHeight; // FBI video display Y-resolution
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FxU32 fbiVideoRefresh; // FBI video refresh rate
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FxU32 fbiVideoColBuffs; // FBI video number of color buffers
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FxU32 fbiVideoAuxBuffs; // FBI video number of Aux buffers
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FxU32 fbiVideoMemOffset; // FBI video memory offset (in pages)
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FxU32 fbiVideoTilesInX; // FBI video memory 32x32 tiles-in-X
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sst1VideoTimingStruct // FBI video resolution
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*fbiVideoStruct; // data structure
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FxU32 fbiVideoDacType; // FBI video dac type detected
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FxU32 fbiMemoryFifoEn; // FBI Memory Fifo enabled
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FxU32 fbiCmdFifoEn; // FBI Command Fifo enabled
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FxU32 fbiLfbLocked; // FBI frame buffer is locked
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FxU32 fbiConfig; // FBI strapping pins
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FxU32 fbiGrxClkFreq; // FBI graphics clock frequency
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FxU32 fbiMemSize; // FBI frame buffer memory (in MBytes)
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FxU32 fbiInitGammaDone; // FBI gamma table initialized
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double fbiGammaRed; // FBI Red gamma value
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double fbiGammaGreen; // FBI Green gamma value
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double fbiGammaBlue; // FBI Blue gamma value
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FxU32 fbiNandTree; // FBI Nand tree delay value
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FxU32 fbiNorTree; // FBI Nor tree delay value
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FxU32 tmuRevision; // TMU revision number (for all TMUs)
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FxU32 tmuFab[MAX_NUM_TMUS]; // TMU Fab ID (for all TMUs)
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FxU32 numberTmus; // Number of TMUs installed
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FxU32 tmuConfig; // TMU configuration bits
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FxU32 tmuGrxClkFreq; // TMU graphics clock frequency
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FxU32 tmuMemSize[MAX_NUM_TMUS]; // TMU texture memory (in MBytes)
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// Registers which cannot be read from the hardware, so we shadow them here
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FxU32 tmuInit0[MAX_NUM_TMUS]; // TMU initialization registers
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FxU32 tmuInit1[MAX_NUM_TMUS]; // TMU initialization registers
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FxU32 fbiInit6; // FBI initialization register
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FxU32 fbiInitEnable; // FBI PCI Configuration register initEnable
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// Misc
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FxU32 sliDetected; // Scanline interleave detected
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FxU32 sliPaired; // Board part of an sli pair
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FxU32 monitorDetected; // Monitor connection detected
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FxU32 *sliSlaveVirtAddr; // Slave virtual address
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// Set to 0 if SLI is not enabled...
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FxU32 initGrxClkDone; // Grapics clock has been initializated
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FxU32 vgaPassthruDisable; // Value to force SST-1 control of monitor
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FxU32 vgaPassthruEnable; // Value to force VGA control of monitor
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FxU32 memFifoStatusLwm;
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// Client setter callbacks
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FxSet32Proc set32;
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// PCI library stuff
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FxU32 mtrrUncacheable; /* 3d register space (all wraps) */
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FxU32 mtrrWriteCombine; /* command fifo/3d lfb */
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SstRegs *sstCSIM;
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SstRegs *sstHW; // pointer to HW
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} sst1DeviceInfoStruct;
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#endif /* !SST1 && !SST96_FIFO */
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#endif /* !__CVGINFO_H__ */
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#endif
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71
swlibs/fxmisc/fxptl.h
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71
swlibs/fxmisc/fxptl.h
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//
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// Define the various device type values. Note that values used by Microsoft
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// Corporation are in the range 0-32767, and 32768-65535 are reserved for use
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// by customers.
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//
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#define FILE_DEVICE_MAPMEM 0x00008000
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//
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// Macro definition for defining IOCTL and FSCTL function control codes. Note
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// that function codes 0-2047 are reserved for Microsoft Corporation, and
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// 2048-4095 are reserved for customers.
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//
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#define MAPMEM_IOCTL_INDEX 0x800
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//
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// Define our own private IOCTL
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//
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#ifndef NT_INCLUDED
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/* xxx The following two typedefs are here to avoid including
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* miniport.h and ntddk.h from the NT DDK from user code because
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* its not always in the build environment.
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*/
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typedef enum
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{
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Internal,
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Isa,
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Eisa,
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MicroChannel,
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TurboChannel,
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PCIBus,
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MaximumInterfaceType
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} INTERFACE_TYPE, *PINTERFACE_TYPE;
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typedef LARGE_INTEGER PHYSICAL_ADDRESS;
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#endif /* !NT_INCLUDED */
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// Our user mode app will pass an initialized structure like this
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// down to the kernel mode driver to map memory.
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typedef struct {
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INTERFACE_TYPE InterfaceType; // Isa, Eisa, etc....
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ULONG BusNumber; // Bus number
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PHYSICAL_ADDRESS BusAddress; // Bus-relative address
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ULONG AddressSpace; // 0 is memory, 1 is I/O
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ULONG Length; // Length of section to map
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} PHYSICAL_MEMORY_INFO, *PPHYSICAL_MEMORY_INFO;
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#define IOCTL_MAPMEM_MAP_USER_PHYSICAL_MEMORY CTL_CODE(FILE_DEVICE_MAPMEM , \
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MAPMEM_IOCTL_INDEX + 0, \
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METHOD_BUFFERED, \
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FILE_ANY_ACCESS)
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/* Passes the linear address to unmap */
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#define IOCTL_MAPMEM_UNMAP_USER_PHYSICAL_MEMORY CTL_CODE(FILE_DEVICE_MAPMEM, \
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MAPMEM_IOCTL_INDEX + 1, \
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METHOD_BUFFERED, \
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FILE_ANY_ACCESS)
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/* Stuff for programming MSRs */
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#define IOCTL_MAPMEM_GET_MSR CTL_CODE(FILE_DEVICE_MAPMEM, \
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MAPMEM_IOCTL_INDEX + 2, \
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METHOD_BUFFERED, \
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FILE_ANY_ACCESS)
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#define IOCTL_MAPMEM_SET_MSR CTL_CODE(FILE_DEVICE_MAPMEM, \
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MAPMEM_IOCTL_INDEX + 3, \
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METHOD_BUFFERED, \
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FILE_ANY_ACCESS)
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39
swlibs/fxmisc/gpioctl.h
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39
swlibs/fxmisc/gpioctl.h
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// gpioctl.h Include file for Generic Port I/O Example Driver
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//
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// Define the IOCTL codes we will use. The IOCTL code contains a command
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// identifier, plus other information about the device, the type of access
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// with which the file must have been opened, and the type of buffering.
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//
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// Robert B. Nelson (Microsoft) March 1, 1993
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// Device type -- in the "User Defined" range."
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#define GPD_TYPE 40000
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// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
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#define IOCTL_GPD_READ_PORT_UCHAR \
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CTL_CODE( GPD_TYPE, 0x900, METHOD_BUFFERED, FILE_READ_ACCESS )
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#define IOCTL_GPD_READ_PORT_USHORT \
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CTL_CODE( GPD_TYPE, 0x901, METHOD_BUFFERED, FILE_READ_ACCESS )
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#define IOCTL_GPD_READ_PORT_ULONG \
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CTL_CODE( GPD_TYPE, 0x902, METHOD_BUFFERED, FILE_READ_ACCESS )
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#define IOCTL_GPD_WRITE_PORT_UCHAR \
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CTL_CODE(GPD_TYPE, 0x910, METHOD_BUFFERED, FILE_WRITE_ACCESS)
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#define IOCTL_GPD_WRITE_PORT_USHORT \
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CTL_CODE(GPD_TYPE, 0x911, METHOD_BUFFERED, FILE_WRITE_ACCESS)
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#define IOCTL_GPD_WRITE_PORT_ULONG \
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CTL_CODE(GPD_TYPE, 0x912, METHOD_BUFFERED, FILE_WRITE_ACCESS)
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typedef struct _GENPORT_WRITE_INPUT {
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ULONG PortNumber; // Port # to write to
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union { // Data to be output to port
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ULONG LongData;
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USHORT ShortData;
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UCHAR CharData;
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};
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} GENPORT_WRITE_INPUT;
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98
swlibs/fxmisc/oeminit.h
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98
swlibs/fxmisc/oeminit.h
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/*
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** Copyright (c) 1995, 3Dfx Interactive, Inc.
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** All Rights Reserved.
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**
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** This is UNPUBLISHED PROPRIETARY SOURCE CODE of 3Dfx Interactive, Inc.;
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** the contents of this file may not be disclosed to third parties, copied or
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** duplicated in any form, in whole or in part, without the prior written
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** permission of 3Dfx Interactive, Inc.
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**
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** RESTRICTED RIGHTS LEGEND:
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** Use, duplication or disclosure by the Government is subject to restrictions
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** as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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** and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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** successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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** rights reserved under the Copyright Laws of the United States.
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*/
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#ifndef __OEMINIT_H__
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#define __OEMINIT_H__
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#define OEMINIT_INVALID_BOARD_ID 0xdeadfeed
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#define OEMINIT_VERSION 0x10001
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#include "3dfx.h"
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#define FX_DLL_DEFINITION
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#include "fxdll.h"
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#include "sst1vid.h"
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#define FX_OEM_CONTROL_ACTIVATE 1
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#define FX_OEM_CONTROL_DEACTIVATE 2
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#define FX_OEM_TVOUT 1
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#define FX_OEM_SLIMASTER 2
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#define FX_OEM_SLISLAVE 3
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#define FX_OEM_FBI_CONFIG_SHIFT 8
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typedef enum {
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OEM_READ_ONLY,
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OEM_WRITE_ONLY,
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OEM_READ_WRITE
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} OemPciIOFlag;
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typedef struct {
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FxU32 regAddress;
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FxU32 sizeInBytes;
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OemPciIOFlag rwFlag;
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} OemPciRegister;
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typedef FxU32 (FX_CALL* PciConfigProc)(OemPciRegister, FxU32, FxU32 *);
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typedef struct {
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GrScreenResolution_t res;
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GrScreenRefresh_t refresh;
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FxU32 depth;
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FxU32 hSyncOn;
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FxU32 hSyncOff;
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FxU32 vSyncOn;
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FxU32 vSyncOff;
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FxU32 hBackPorch;
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FxU32 vBackPorch;
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FxU32 xDimension;
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FxU32 yDimension;
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float clkFreq16bpp;
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float clkFreq24bpp;
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} OemVideoTimingInfo;
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typedef struct {
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FxU32 version; /* Version for this structure */
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FxU32 vendorID; /* PCI Vendor ID field */
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FxU32 subvendorID; /* PCI sub Vendor ID field */
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FxU32 deviceID; /* PCI Device ID field */
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FxU32 boardID; /* Board ID: defined for Voodoo2 only!!! */
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FxU32 *linearAddress; /* address for primary board */
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FxU32 *slaveAddress; /* address for slave board */
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PciConfigProc fxoemPciWriteConfig;
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PciConfigProc fxoemPciReadConfig;
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OemVideoTimingInfo vid;
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FxU32 reserved[42];
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} OemInitInfo;
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitMapBoard(OemInitInfo *oem);
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FX_EXPORT FxI32 FX_CSTYLE fxoemGet(FxU32 pname, FxU32 plength, FxI32 *params);
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitVideoTiming(OemVideoTimingInfo *vid);
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitSetVideo(OemInitInfo *oem);
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FX_EXPORT FxU32 FX_CSTYLE fxoemRestoreVideo(OemInitInfo *oem);
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FX_EXPORT FxU32 FX_CSTYLE fxoemControl(FxU32 mode);
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FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlP(OemInitInfo* oemInfo);
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FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlWrite(OemInitInfo* oemInfo,
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FxU32* writeBuffer);
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typedef FxU32 (FX_CALL* FxOemSwapControlP)(OemInitInfo* oemInfo);
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typedef FxU32 (FX_CALL* FxOemSwapControlWrite)(OemInitInfo* oemInfo,
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FxU32* writeBuffer);
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#endif __OEMINIT_H__
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