diff --git a/swlibs/fxmisc/ddglobal.h b/swlibs/fxmisc/ddglobal.h new file mode 100644 index 0000000..b98ada1 --- /dev/null +++ b/swlibs/fxmisc/ddglobal.h @@ -0,0 +1,138 @@ +/* + * ddglobal.h placeholder for Glide3x (SST1, SST96, CVG) + * + * Copyright (c) 2004 - Daniel Borca + * Email : dborca@users.sourceforge.net + * Web : http://www.geocities.com/dborca + */ + + +#ifndef DDGLOBAL_H_included + +#define ddgetenv(A) getenv(A) +#define ddatoi(A) atoi(A) +#define ddftol(A) ((long)(A)) +#define dd_itof_inv(A) (1.0f/(float)(A)) +#define ddatof(A) atof(A) +#define ddpow(A, B) pow(A, B) +#define ddsscanf(A, B, C) sscanf(A, B, C) + +/* + * Perhaps this file should be personalized for each ASIC, + * and then moved into the respective glide3x branches... + */ +#ifndef __CVGINFO_H__ + +#if defined(SST1) || defined(SST96_FIFO) + +#include + +#else /* !SST1 && !SST96_FIFO */ + +// Video timing data structure +typedef struct { + FxU32 hSyncOn; + FxU32 hSyncOff; + FxU32 vSyncOn; + FxU32 vSyncOff; + FxU32 hBackPorch; + FxU32 vBackPorch; + FxU32 xDimension; + FxU32 yDimension; + FxU32 refreshRate; + FxU32 miscCtrl; + FxU32 memOffset; + FxU32 tilesInX; + FxU32 vFifoThreshold; + FxBool video16BPPIsOK; + FxBool video24BPPIsOK; + float clkFreq16bpp; + float clkFreq24bpp; +} sst1VideoTimingStruct; + +/* Init code client callbacks to allow the init code to use the client + * command fifo management code to do writes etc. + */ +typedef void (*FxSet32Proc)(volatile FxU32* const addr, const FxU32 val); + +/* +** CVG Device Information Structure +** +*/ +// Initialization and configuration data structure +typedef struct { + FxU32 size; // size of this structure + SstRegs *virtAddr[2]; // virtual memory base address + FxU32 physAddr[2]; // physical memory base address + FxU32 deviceNumber; // PCI device number + FxU32 vendorID; // PCI vendor ID + FxU32 deviceID; // PCI device ID + + FxU32 fbiRevision; // FBI revision number + FxU32 fbiFab; // FBI Fab ID + FxU32 fbiBoardID; // FBI board ID (poweron strapping bits) + FxU32 fbiVideo16BPP; // FBI video display mode + FxU32 fbiVideoWidth; // FBI video display X-resolution + FxU32 fbiVideoHeight; // FBI video display Y-resolution + FxU32 fbiVideoRefresh; // FBI video refresh rate + FxU32 fbiVideoColBuffs; // FBI video number of color buffers + FxU32 fbiVideoAuxBuffs; // FBI video number of Aux buffers + FxU32 fbiVideoMemOffset; // FBI video memory offset (in pages) + FxU32 fbiVideoTilesInX; // FBI video memory 32x32 tiles-in-X + sst1VideoTimingStruct // FBI video resolution + *fbiVideoStruct; // data structure + FxU32 fbiVideoDacType; // FBI video dac type detected + FxU32 fbiMemoryFifoEn; // FBI Memory Fifo enabled + FxU32 fbiCmdFifoEn; // FBI Command Fifo enabled + FxU32 fbiLfbLocked; // FBI frame buffer is locked + FxU32 fbiConfig; // FBI strapping pins + FxU32 fbiGrxClkFreq; // FBI graphics clock frequency + FxU32 fbiMemSize; // FBI frame buffer memory (in MBytes) + FxU32 fbiInitGammaDone; // FBI gamma table initialized + double fbiGammaRed; // FBI Red gamma value + double fbiGammaGreen; // FBI Green gamma value + double fbiGammaBlue; // FBI Blue gamma value + FxU32 fbiNandTree; // FBI Nand tree delay value + FxU32 fbiNorTree; // FBI Nor tree delay value + + FxU32 tmuRevision; // TMU revision number (for all TMUs) + FxU32 tmuFab[MAX_NUM_TMUS]; // TMU Fab ID (for all TMUs) + FxU32 numberTmus; // Number of TMUs installed + FxU32 tmuConfig; // TMU configuration bits + FxU32 tmuGrxClkFreq; // TMU graphics clock frequency + FxU32 tmuMemSize[MAX_NUM_TMUS]; // TMU texture memory (in MBytes) + + // Registers which cannot be read from the hardware, so we shadow them here + FxU32 tmuInit0[MAX_NUM_TMUS]; // TMU initialization registers + FxU32 tmuInit1[MAX_NUM_TMUS]; // TMU initialization registers + FxU32 fbiInit6; // FBI initialization register + FxU32 fbiInitEnable; // FBI PCI Configuration register initEnable + + // Misc + FxU32 sliDetected; // Scanline interleave detected + FxU32 sliPaired; // Board part of an sli pair + FxU32 monitorDetected; // Monitor connection detected + FxU32 *sliSlaveVirtAddr; // Slave virtual address + // Set to 0 if SLI is not enabled... + FxU32 initGrxClkDone; // Grapics clock has been initializated + FxU32 vgaPassthruDisable; // Value to force SST-1 control of monitor + FxU32 vgaPassthruEnable; // Value to force VGA control of monitor + FxU32 memFifoStatusLwm; + + // Client setter callbacks + FxSet32Proc set32; + + // PCI library stuff + FxU32 mtrrUncacheable; /* 3d register space (all wraps) */ + FxU32 mtrrWriteCombine; /* command fifo/3d lfb */ + + + SstRegs *sstCSIM; + SstRegs *sstHW; // pointer to HW +} sst1DeviceInfoStruct; + +#endif /* !SST1 && !SST96_FIFO */ + +#endif /* !__CVGINFO_H__ */ + +#endif diff --git a/swlibs/fxmisc/fxptl.h b/swlibs/fxmisc/fxptl.h new file mode 100644 index 0000000..251e1e9 --- /dev/null +++ b/swlibs/fxmisc/fxptl.h @@ -0,0 +1,71 @@ +// +// Define the various device type values. Note that values used by Microsoft +// Corporation are in the range 0-32767, and 32768-65535 are reserved for use +// by customers. +// + +#define FILE_DEVICE_MAPMEM 0x00008000 + + + +// +// Macro definition for defining IOCTL and FSCTL function control codes. Note +// that function codes 0-2047 are reserved for Microsoft Corporation, and +// 2048-4095 are reserved for customers. +// + +#define MAPMEM_IOCTL_INDEX 0x800 + + +// +// Define our own private IOCTL +// + +#ifndef NT_INCLUDED +/* xxx The following two typedefs are here to avoid including + * miniport.h and ntddk.h from the NT DDK from user code because + * its not always in the build environment. + */ +typedef enum +{ + Internal, + Isa, + Eisa, + MicroChannel, + TurboChannel, + PCIBus, + MaximumInterfaceType +} INTERFACE_TYPE, *PINTERFACE_TYPE; +typedef LARGE_INTEGER PHYSICAL_ADDRESS; +#endif /* !NT_INCLUDED */ + +// Our user mode app will pass an initialized structure like this +// down to the kernel mode driver to map memory. +typedef struct { + INTERFACE_TYPE InterfaceType; // Isa, Eisa, etc.... + ULONG BusNumber; // Bus number + PHYSICAL_ADDRESS BusAddress; // Bus-relative address + ULONG AddressSpace; // 0 is memory, 1 is I/O + ULONG Length; // Length of section to map +} PHYSICAL_MEMORY_INFO, *PPHYSICAL_MEMORY_INFO; + +#define IOCTL_MAPMEM_MAP_USER_PHYSICAL_MEMORY CTL_CODE(FILE_DEVICE_MAPMEM , \ + MAPMEM_IOCTL_INDEX + 0, \ + METHOD_BUFFERED, \ + FILE_ANY_ACCESS) + +/* Passes the linear address to unmap */ +#define IOCTL_MAPMEM_UNMAP_USER_PHYSICAL_MEMORY CTL_CODE(FILE_DEVICE_MAPMEM, \ + MAPMEM_IOCTL_INDEX + 1, \ + METHOD_BUFFERED, \ + FILE_ANY_ACCESS) + +/* Stuff for programming MSRs */ +#define IOCTL_MAPMEM_GET_MSR CTL_CODE(FILE_DEVICE_MAPMEM, \ + MAPMEM_IOCTL_INDEX + 2, \ + METHOD_BUFFERED, \ + FILE_ANY_ACCESS) +#define IOCTL_MAPMEM_SET_MSR CTL_CODE(FILE_DEVICE_MAPMEM, \ + MAPMEM_IOCTL_INDEX + 3, \ + METHOD_BUFFERED, \ + FILE_ANY_ACCESS) diff --git a/swlibs/fxmisc/gpioctl.h b/swlibs/fxmisc/gpioctl.h new file mode 100644 index 0000000..4f944de --- /dev/null +++ b/swlibs/fxmisc/gpioctl.h @@ -0,0 +1,39 @@ +// gpioctl.h Include file for Generic Port I/O Example Driver +// +// Define the IOCTL codes we will use. The IOCTL code contains a command +// identifier, plus other information about the device, the type of access +// with which the file must have been opened, and the type of buffering. +// +// Robert B. Nelson (Microsoft) March 1, 1993 + +// Device type -- in the "User Defined" range." +#define GPD_TYPE 40000 + +// The IOCTL function codes from 0x800 to 0xFFF are for customer use. + +#define IOCTL_GPD_READ_PORT_UCHAR \ + CTL_CODE( GPD_TYPE, 0x900, METHOD_BUFFERED, FILE_READ_ACCESS ) + +#define IOCTL_GPD_READ_PORT_USHORT \ + CTL_CODE( GPD_TYPE, 0x901, METHOD_BUFFERED, FILE_READ_ACCESS ) + +#define IOCTL_GPD_READ_PORT_ULONG \ + CTL_CODE( GPD_TYPE, 0x902, METHOD_BUFFERED, FILE_READ_ACCESS ) + +#define IOCTL_GPD_WRITE_PORT_UCHAR \ + CTL_CODE(GPD_TYPE, 0x910, METHOD_BUFFERED, FILE_WRITE_ACCESS) + +#define IOCTL_GPD_WRITE_PORT_USHORT \ + CTL_CODE(GPD_TYPE, 0x911, METHOD_BUFFERED, FILE_WRITE_ACCESS) + +#define IOCTL_GPD_WRITE_PORT_ULONG \ + CTL_CODE(GPD_TYPE, 0x912, METHOD_BUFFERED, FILE_WRITE_ACCESS) + +typedef struct _GENPORT_WRITE_INPUT { + ULONG PortNumber; // Port # to write to + union { // Data to be output to port + ULONG LongData; + USHORT ShortData; + UCHAR CharData; + }; +} GENPORT_WRITE_INPUT; diff --git a/swlibs/fxmisc/oeminit.h b/swlibs/fxmisc/oeminit.h new file mode 100644 index 0000000..29e407c --- /dev/null +++ b/swlibs/fxmisc/oeminit.h @@ -0,0 +1,98 @@ +/* +** Copyright (c) 1995, 3Dfx Interactive, Inc. +** All Rights Reserved. +** +** This is UNPUBLISHED PROPRIETARY SOURCE CODE of 3Dfx Interactive, Inc.; +** the contents of this file may not be disclosed to third parties, copied or +** duplicated in any form, in whole or in part, without the prior written +** permission of 3Dfx Interactive, Inc. +** +** RESTRICTED RIGHTS LEGEND: +** Use, duplication or disclosure by the Government is subject to restrictions +** as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data +** and Computer Software clause at DFARS 252.227-7013, and/or in similar or +** successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished - +** rights reserved under the Copyright Laws of the United States. +*/ + +#ifndef __OEMINIT_H__ +#define __OEMINIT_H__ + +#define OEMINIT_INVALID_BOARD_ID 0xdeadfeed +#define OEMINIT_VERSION 0x10001 + +#include "3dfx.h" +#define FX_DLL_DEFINITION +#include "fxdll.h" +#include "sst1vid.h" + +#define FX_OEM_CONTROL_ACTIVATE 1 +#define FX_OEM_CONTROL_DEACTIVATE 2 + +#define FX_OEM_TVOUT 1 +#define FX_OEM_SLIMASTER 2 +#define FX_OEM_SLISLAVE 3 + +#define FX_OEM_FBI_CONFIG_SHIFT 8 + +typedef enum { + OEM_READ_ONLY, + OEM_WRITE_ONLY, + OEM_READ_WRITE +} OemPciIOFlag; + +typedef struct { + FxU32 regAddress; + FxU32 sizeInBytes; + OemPciIOFlag rwFlag; +} OemPciRegister; + +typedef FxU32 (FX_CALL* PciConfigProc)(OemPciRegister, FxU32, FxU32 *); + +typedef struct { + GrScreenResolution_t res; + GrScreenRefresh_t refresh; + FxU32 depth; + FxU32 hSyncOn; + FxU32 hSyncOff; + FxU32 vSyncOn; + FxU32 vSyncOff; + FxU32 hBackPorch; + FxU32 vBackPorch; + FxU32 xDimension; + FxU32 yDimension; + float clkFreq16bpp; + float clkFreq24bpp; +} OemVideoTimingInfo; + +typedef struct { + FxU32 version; /* Version for this structure */ + FxU32 vendorID; /* PCI Vendor ID field */ + FxU32 subvendorID; /* PCI sub Vendor ID field */ + FxU32 deviceID; /* PCI Device ID field */ + FxU32 boardID; /* Board ID: defined for Voodoo2 only!!! */ + FxU32 *linearAddress; /* address for primary board */ + FxU32 *slaveAddress; /* address for slave board */ + PciConfigProc fxoemPciWriteConfig; + PciConfigProc fxoemPciReadConfig; + OemVideoTimingInfo vid; + FxU32 reserved[42]; +} OemInitInfo; + +FX_EXPORT FxU32 FX_CSTYLE fxoemInitMapBoard(OemInitInfo *oem); +FX_EXPORT FxI32 FX_CSTYLE fxoemGet(FxU32 pname, FxU32 plength, FxI32 *params); +FX_EXPORT FxU32 FX_CSTYLE fxoemInitVideoTiming(OemVideoTimingInfo *vid); +FX_EXPORT FxU32 FX_CSTYLE fxoemInitSetVideo(OemInitInfo *oem); +FX_EXPORT FxU32 FX_CSTYLE fxoemRestoreVideo(OemInitInfo *oem); +FX_EXPORT FxU32 FX_CSTYLE fxoemControl(FxU32 mode); + +FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlP(OemInitInfo* oemInfo); +FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlWrite(OemInitInfo* oemInfo, + FxU32* writeBuffer); + +typedef FxU32 (FX_CALL* FxOemSwapControlP)(OemInitInfo* oemInfo); +typedef FxU32 (FX_CALL* FxOemSwapControlWrite)(OemInitInfo* oemInfo, + FxU32* writeBuffer); + +#endif __OEMINIT_H__ +