458 lines
17 KiB
C
458 lines
17 KiB
C
/* V2MemTest - A CLI Tool to test & fix Voodoo² TMU System
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* Copyright (C) 2026 ChaCha
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "cvg.h"
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#include <glide.h>
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#include "sst1init.h"
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#include "fxpci.h"
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#include "Utils.h"
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#include "V2MemTest.h"
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#include "FaultSources.h"
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#include "Utils.h"
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#include "Draw.h"
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#include "Test_Control.h"
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static void
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WriteTex( FxU32 * const sst,
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SstRegs * const sstregs,
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const uint32_t baseAddr,
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const char ucNumTMU,
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const uint32_t Val1,
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const uint32_t Val2)
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{
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/* set base mem @ */
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ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (baseAddr>>3));
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/* set @ to first line, using bits 00..31*/
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volatile const FxU32 *texAddrBlank
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= (ucNumTMU<<(21-2))
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+ (((FxU32)0)<<(17-2)) /*LOD0*/
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+ (FxU32 *)SST_TEX_ADDRESS(sst);
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/* write the value */
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ISET(texAddrBlank[0], Val1);
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/* set @ to second line, to use bits 32..63*/
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volatile const FxU32 *texAddrBlank2
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= (ucNumTMU<<(21-2))
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+ (((FxU32)0)<<(17-2)) /*LOD0*/
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+ (1<<(9-2))
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+ (FxU32 *)SST_TEX_ADDRESS(sst);
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/* write the value */
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ISET(texAddrBlank2[0], Val2);
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}
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unsigned long
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CheckRead( FxU32 * const sst,
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SstRegs * const sstregs,
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const uint32_t baseAddr,
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const char ucNumTMU,
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const unsigned char bNominal,
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const uint32_t Val1,
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const uint32_t Val2,
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const uint32_t ValOther1,
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const uint32_t ValOther2,
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def_sFaultSourceScoreRec* const pFaultSrcCtx)
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{
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unsigned long NbErr=0;
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const unsigned char nBank = (baseAddr<0x200000) ? 0 : 1;
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const def_eFaultSource TMUTexWE = (ucNumTMU == 0) ? U9_TMU0_TEX_WE : U8_TMU1_TEX_WE;
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const def_eFaultSource TMUTexCAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS0 : U8_TMU1_TEX_CAS0;
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const def_eFaultSource TMUTexCAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS1 : U8_TMU1_TEX_CAS1;
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const def_eFaultSource TMUTexCAS2 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS2 : U8_TMU1_TEX_CAS2;
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const def_eFaultSource TMUTexCAS3 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS3 : U8_TMU1_TEX_CAS3;
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const def_eFaultSource _TMUTexRAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS0 : U8_TMU1_TEX_RAS0;
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const def_eFaultSource _TMUTexRAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS1 : U8_TMU1_TEX_RAS1;
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const def_eFaultSource TMUTexRASCurrent = (nBank == 0) ? _TMUTexRAS0 : _TMUTexRAS1;
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const def_eFaultSource _MEMChip_B0_0_CASL = (ucNumTMU == 0) ? U14_CASL : U13_CASL;
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const def_eFaultSource _MEMChip_B0_1_CASL = (ucNumTMU == 0) ? U12_CASL : U11_CASL;
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const def_eFaultSource _MEMChip_B0_2_CASL = (ucNumTMU == 0) ? U18_CASL : U16_CASL;
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const def_eFaultSource _MEMChip_B0_3_CASL = (ucNumTMU == 0) ? U17_CASL : U15_CASL;
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const def_eFaultSource _MEMChip_B1_0_CASL = (ucNumTMU == 0) ? U23_CASL : U27_CASL;
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const def_eFaultSource _MEMChip_B1_1_CASL = (ucNumTMU == 0) ? U24_CASL : U28_CASL;
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const def_eFaultSource _MEMChip_B1_2_CASL = (ucNumTMU == 0) ? U25_CASL : U29_CASL;
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const def_eFaultSource _MEMChip_B1_3_CASL = (ucNumTMU == 0) ? U26_CASL : U30_CASL;
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const def_eFaultSource MEMChip_0_CASL = (nBank == 0) ? _MEMChip_B0_0_CASL : _MEMChip_B1_0_CASL;
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const def_eFaultSource MEMChip_1_CASL = (nBank == 0) ? _MEMChip_B0_1_CASL : _MEMChip_B1_1_CASL;
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const def_eFaultSource MEMChip_2_CASL = (nBank == 0) ? _MEMChip_B0_2_CASL : _MEMChip_B1_2_CASL;
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const def_eFaultSource MEMChip_3_CASL = (nBank == 0) ? _MEMChip_B0_3_CASL : _MEMChip_B1_3_CASL;
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const def_eFaultSource _MEMChip_B0_0_CASH = (ucNumTMU == 0) ? U14_CASH : U13_CASH;
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const def_eFaultSource _MEMChip_B0_1_CASH = (ucNumTMU == 0) ? U12_CASH : U11_CASH;
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const def_eFaultSource _MEMChip_B0_2_CASH = (ucNumTMU == 0) ? U18_CASH : U16_CASH;
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const def_eFaultSource _MEMChip_B0_3_CASH = (ucNumTMU == 0) ? U17_CASH : U15_CASH;
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const def_eFaultSource _MEMChip_B1_0_CASH = (ucNumTMU == 0) ? U23_CASH : U27_CASH;
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const def_eFaultSource _MEMChip_B1_1_CASH = (ucNumTMU == 0) ? U24_CASH : U28_CASH;
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const def_eFaultSource _MEMChip_B1_2_CASH = (ucNumTMU == 0) ? U25_CASH : U29_CASH;
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const def_eFaultSource _MEMChip_B1_3_CASH = (ucNumTMU == 0) ? U26_CASH : U30_CASH;
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const def_eFaultSource MEMChip_0_CASH = (nBank == 0) ? _MEMChip_B0_0_CASH : _MEMChip_B1_0_CASH;
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const def_eFaultSource MEMChip_1_CASH = (nBank == 0) ? _MEMChip_B0_1_CASH : _MEMChip_B1_1_CASH;
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const def_eFaultSource MEMChip_2_CASH = (nBank == 0) ? _MEMChip_B0_2_CASH : _MEMChip_B1_2_CASH;
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const def_eFaultSource MEMChip_3_CASH = (nBank == 0) ? _MEMChip_B0_3_CASH : _MEMChip_B1_3_CASH;
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const def_eFaultSource _MEMChip_B0_0_RAS = (ucNumTMU == 0) ? U14_RAS : U13_RAS;
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const def_eFaultSource _MEMChip_B0_1_RAS = (ucNumTMU == 0) ? U12_RAS : U11_RAS;
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const def_eFaultSource _MEMChip_B0_2_RAS = (ucNumTMU == 0) ? U18_RAS : U16_RAS;
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const def_eFaultSource _MEMChip_B0_3_RAS = (ucNumTMU == 0) ? U17_RAS : U15_RAS;
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const def_eFaultSource _MEMChip_B1_0_RAS = (ucNumTMU == 0) ? U23_RAS : U27_RAS;
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const def_eFaultSource _MEMChip_B1_1_RAS = (ucNumTMU == 0) ? U24_RAS : U28_RAS;
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const def_eFaultSource _MEMChip_B1_2_RAS = (ucNumTMU == 0) ? U25_RAS : U29_RAS;
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const def_eFaultSource _MEMChip_B1_3_RAS = (ucNumTMU == 0) ? U26_RAS : U30_RAS;
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const def_eFaultSource MEMChip_0_RAS = (nBank == 0) ? _MEMChip_B0_0_RAS : _MEMChip_B1_0_RAS;
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const def_eFaultSource MEMChip_1_RAS = (nBank == 0) ? _MEMChip_B0_1_RAS : _MEMChip_B1_1_RAS;
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const def_eFaultSource MEMChip_2_RAS = (nBank == 0) ? _MEMChip_B0_2_RAS : _MEMChip_B1_2_RAS;
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const def_eFaultSource MEMChip_3_RAS = (nBank == 0) ? _MEMChip_B0_3_RAS : _MEMChip_B1_3_RAS;
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const def_eFaultSource _MEMChip_B0_0_WE = (ucNumTMU == 0) ? U14_WE : U13_WE;
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const def_eFaultSource _MEMChip_B0_1_WE = (ucNumTMU == 0) ? U12_WE : U11_WE;
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const def_eFaultSource _MEMChip_B0_2_WE = (ucNumTMU == 0) ? U18_WE : U16_WE;
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const def_eFaultSource _MEMChip_B0_3_WE = (ucNumTMU == 0) ? U17_WE : U15_WE;
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const def_eFaultSource _MEMChip_B1_0_WE = (ucNumTMU == 0) ? U23_WE : U27_WE;
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const def_eFaultSource _MEMChip_B1_1_WE = (ucNumTMU == 0) ? U24_WE : U28_WE;
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const def_eFaultSource _MEMChip_B1_2_WE = (ucNumTMU == 0) ? U25_WE : U29_WE;
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const def_eFaultSource _MEMChip_B1_3_WE = (ucNumTMU == 0) ? U26_WE : U30_WE;
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const def_eFaultSource MEMChip_0_WE = (nBank == 0) ? _MEMChip_B0_0_WE : _MEMChip_B1_0_WE;
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const def_eFaultSource MEMChip_1_WE = (nBank == 0) ? _MEMChip_B0_1_WE : _MEMChip_B1_1_WE;
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const def_eFaultSource MEMChip_2_WE = (nBank == 0) ? _MEMChip_B0_2_WE : _MEMChip_B1_2_WE;
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const def_eFaultSource MEMChip_3_WE = (nBank == 0) ? _MEMChip_B0_3_WE : _MEMChip_B1_3_WE;
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const def_eFaultSource _RES_RAS0 = (ucNumTMU == 0) ? R118 : R115;
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const def_eFaultSource _RES_RAS1 = (ucNumTMU == 0) ? R149 : R150;
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const def_eFaultSource RES_RAS = (nBank == 0) ? _RES_RAS0 : _RES_RAS1;
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const def_eFaultSource RES_CAS = (ucNumTMU == 0) ? RA36 : RA32;
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const def_eFaultSource RES_WE = (ucNumTMU == 0) ? R117 : R114;
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clearScreen(sstregs,0x00000000,2,2);
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/* set to mem addr */
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ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (baseAddr >> 3));
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/* draw a 2x2 square */
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drawSquare(sstregs, ucNumTMU, 0, 0, 2);
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sst1InitIdle(sst);
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/* first line, to use bits 00..31 */
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const uint32_t L1 = IGET(sst[(SST_LFB_ADDR>>2) + 0]);
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/* second line, to use bits 32..63 */
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const uint32_t L2 = IGET(sst[(SST_LFB_ADDR>>2) + (2048>>2) + 0]);
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const uint32_t ErrorMark_L1 = (L1 ^ Val1);
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const uint32_t ErrorMark_L2 = (L2 ^ Val2);
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const uint32_t ErrorMark_L1_Other = (L1 ^ ValOther1);
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const uint32_t ErrorMark_L2_Other = (L2 ^ ValOther2);
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if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 4)
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{
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NbErr++;
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/* If we are reading the value of the other Bank
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* then it has to be a bank select problem*/
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if(!bNominal && count_bit32(ErrorMark_L1_Other & 0x0000FFFF) < 4)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_0_RAS, 2.0);
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}
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else
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{
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/* WE can fail only in case of plain failure */
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if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 8)
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{
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/*WE are shared accross all memory chips so
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* we divide the weight by 4.*/
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FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_0_WE, 1.0);
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}
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unsigned char bLSBFailed = false;
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unsigned char bMSBFailed = false;
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if(count_bit32(ErrorMark_L1 & 0x000000FF) > 2)
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{
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/*CAS are shared accross multiple memory chips so
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* we divide the weight by 2.*/
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS0, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+1, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_0_CASL, 1.0);
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bLSBFailed = true;
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}
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if(count_bit32(ErrorMark_L1 & 0x0000FF00) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS1, 1.0/2);;
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+2, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_0_CASH, 1.0);
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bMSBFailed = true;
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}
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/* RAS is declared failed only if both CAS failed */
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if(bLSBFailed && bMSBFailed)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_0_RAS, 4.0);
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}
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}
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}
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if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 4)
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{
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NbErr++;
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if(!bNominal && count_bit32(ErrorMark_L1_Other & 0xFFFF0000) < 4)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_1_RAS, 2.0);
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}
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else
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{
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if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 8)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_1_WE, 1.0);
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}
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unsigned char bLSBFailed = false;
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unsigned char bMSBFailed = false;
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if(count_bit32(ErrorMark_L1 & 0x00FF0000) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS0, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+1, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_1_CASL, 1.0);
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bLSBFailed = true;
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}
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if(count_bit32(ErrorMark_L1 & 0xFF000000) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS1, 1.0/2);;
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+2, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_1_CASH, 1.0);
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bMSBFailed = true;
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}
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if(bLSBFailed && bMSBFailed)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_1_RAS, 4.0);
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}
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}
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}
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if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 4)
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{
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NbErr++;
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if(!bNominal && count_bit32(ErrorMark_L2_Other & 0x0000FFFF) < 4)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_2_RAS, 2.0);
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}
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else
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{
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if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 8)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_2_WE, 1.0);
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}
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unsigned char bLSBFailed = false;
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unsigned char bMSBFailed = false;
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if(count_bit32(ErrorMark_L2 & 0x000000FF) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS2, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+3, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_2_CASL, 1.0);
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bLSBFailed = true;
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}
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if(count_bit32(ErrorMark_L2 & 0x0000FF00) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS3, 1.0/2);;
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+4, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_2_CASH, 1.0);
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bMSBFailed = true;
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}
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if(bLSBFailed && bMSBFailed)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_2_RAS, 4.0);
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}
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}
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}
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if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 4)
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{
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NbErr++;
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if(!bNominal && count_bit32(ErrorMark_L2_Other & 0xFFFF0000) < 4)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_3_RAS, 2.0);
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}
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else
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{
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if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 8)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_3_WE, 1.0);
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}
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unsigned char bLSBFailed = false;
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unsigned char bMSBFailed = false;
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if(count_bit32(ErrorMark_L2 & 0x00FF0000) > 2)
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{
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FaultSource_addScore(pFaultSrcCtx, TMUTexCAS2, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, RES_CAS+3, 1.0/2);
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FaultSource_addScore(pFaultSrcCtx, MEMChip_3_CASL, 1.0);
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bLSBFailed = true;
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}
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if(count_bit32(ErrorMark_L2 & 0xFF000000) > 2)
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|
{
|
|
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS3, 1.0/2);;
|
|
FaultSource_addScore(pFaultSrcCtx, RES_CAS+4, 1.0/2);
|
|
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_CASH, 1.0);
|
|
bMSBFailed = true;
|
|
}
|
|
|
|
if(bLSBFailed && bMSBFailed)
|
|
{
|
|
FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0);
|
|
FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0);
|
|
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_RAS, 4.0);
|
|
}
|
|
}
|
|
}
|
|
|
|
return NbErr;
|
|
}
|
|
|
|
unsigned long
|
|
TestControl( sst1DeviceInfoStruct * const devInfo,
|
|
FxU32 * const sst,
|
|
SstRegs * const sstregs,
|
|
const char ucNumTMU,
|
|
const unsigned char RamSizeMB,
|
|
def_sFaultSourceScoreRec * const pFaultSrcCtx)
|
|
{
|
|
unsigned long NbErr=0;
|
|
|
|
sst1InitIdle(sst);
|
|
unsigned long _trexInit0 = IGET(SST_TREX(sstregs,ucNumTMU)->trexInit0);
|
|
devInfo->tmuInit0[(int)ucNumTMU] = SST_TREXINIT0_DEFAULT ;
|
|
ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]);
|
|
sst1InitIdle(sst);
|
|
|
|
/* set downstream TMUs to passthrough */
|
|
for (int i=0; i<ucNumTMU; i++)
|
|
ISET(SST_TREX(sstregs,i)->textureMode, SST_TC_PASS | SST_TCA_PASS);
|
|
|
|
const uint32_t TestVal1 = get_notnull_random_balanced_mByte();
|
|
logT("TestVal1 = %08X\n",TestVal1);
|
|
|
|
uint32_t TestVal2 = 0;
|
|
do
|
|
{
|
|
TestVal2 = get_notnull_random_balanced_mByte();
|
|
}
|
|
while((count_bit32((TestVal2 ^ TestVal1)) < 12));
|
|
logT("TestVal2 = %08X\n",TestVal2);
|
|
|
|
uint32_t TestValBlank1 = 0;
|
|
do
|
|
{
|
|
TestValBlank1 = get_notnull_random_balanced_mByte();
|
|
}
|
|
while( (count_bit32((TestValBlank1 ^ TestVal1) & 0x0000FFFF) < 6)
|
|
|| (count_bit32((TestValBlank1 ^ TestVal1) & 0xFFFF0000) < 6)
|
|
|| (count_bit32((TestValBlank1 ^ TestVal2)) < 12));
|
|
logT("TestValBlank1 = %08X\n", TestValBlank1);
|
|
|
|
uint32_t TestValBlank2 = 0;
|
|
do
|
|
{
|
|
TestValBlank2 = get_notnull_random_balanced_mByte();
|
|
}
|
|
while( (count_bit32((TestValBlank2 ^ TestVal2) & 0x0000FFFF) < 6)
|
|
|| (count_bit32((TestValBlank2 ^ TestVal2) & 0xFFFF0000) < 6)
|
|
|| (count_bit32((TestValBlank2 ^ TestValBlank1)) < 12)
|
|
|| (count_bit32((TestValBlank2 ^ TestVal1)) < 12));
|
|
logT("TestValBlank2 = %08X\n", TestValBlank2);
|
|
|
|
/* write initial Values */
|
|
/* Bank 0*/
|
|
WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestValBlank1, TestValBlank2);
|
|
/* Bank 1*/
|
|
if(RamSizeMB>2)
|
|
{
|
|
WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestValBlank1, TestValBlank2);
|
|
}
|
|
|
|
/* write to Bank 0 */
|
|
WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestVal1, TestVal2);
|
|
|
|
/* read and check Bank 0 (nominal check)*/
|
|
NbErr += CheckRead(sst, sstregs, 0x000000, ucNumTMU,
|
|
true, TestVal1, TestVal2, TestValBlank1, TestValBlank2, pFaultSrcCtx);
|
|
/* if Bank 1 available*/
|
|
if(RamSizeMB>2)
|
|
{
|
|
/* read and check Bank 1(no modification check)*/
|
|
NbErr += CheckRead(sst, sstregs, 0x200000, ucNumTMU,
|
|
false, TestValBlank1, TestValBlank2, TestVal1, TestVal2, pFaultSrcCtx);
|
|
|
|
/* write initial Values */
|
|
/* Bank 0*/
|
|
WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestValBlank1, TestValBlank2);
|
|
/* Bank 1*/
|
|
if(RamSizeMB>2)
|
|
{
|
|
WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestValBlank1, TestValBlank2);
|
|
}
|
|
|
|
/* write to Bank 1 */
|
|
WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestVal1, TestVal2);
|
|
|
|
/* read and check Bank 1 (nominal check)*/
|
|
NbErr += CheckRead(sst, sstregs, 0x200000, ucNumTMU,
|
|
true, TestVal1, TestVal2, TestValBlank1, TestValBlank2, pFaultSrcCtx);
|
|
|
|
/* read and check Bank 0 (no modification check)*/
|
|
NbErr += CheckRead(sst, sstregs, 0x000000, ucNumTMU,
|
|
false, TestValBlank1, TestValBlank2, TestVal1, TestVal2, pFaultSrcCtx);
|
|
}
|
|
|
|
clearScreen(sstregs,0x00000000,2,2);
|
|
|
|
sst1InitIdle(sst);
|
|
devInfo->tmuInit0[(int)ucNumTMU] = _trexInit0;
|
|
ISET(SST_TREX(sst,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]);
|
|
sst1InitIdle(sst);
|
|
|
|
return NbErr;
|
|
}
|