/*  V2MemTest - A CLI Tool to test & fix Voodoo² TMU System
*   Copyright (C) 2026  ChaCha
*
*   This program is free software: you can redistribute it and/or modify
*   it under the terms of the GNU General Public License as published by
*   the Free Software Foundation, either version 3 of the License, or
*   (at your option) any later version.
*
*   This program is distributed in the hope that it will be useful,
*   but WITHOUT ANY WARRANTY; without even the implied warranty of
*   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*   GNU General Public License for more details.
*
*   You should have received a copy of the GNU General Public License
*   along with this program.  If not, see <https://www.gnu.org/licenses/>.
*/
#include <stdint.h>
#include <stdio.h>

#include "cvg.h" 
#include <glide.h>
#include "sst1init.h"
#include "fxpci.h"

#include "Utils.h"
#include "V2MemTest.h"
#include "FaultSources.h"
#include "Utils.h"
#include "Draw.h"

#include "Test_Control.h"

static void 
WriteTex(	FxU32 * const sst,
			SstRegs * const sstregs,
			const uint32_t baseAddr,
			const char ucNumTMU,
			const uint32_t Val1,
			const uint32_t Val2)
{
	/* set base mem @ */
	ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (baseAddr>>3));
	/* set @ to first line, using bits 00..31*/
	volatile const FxU32 *texAddrBlank
		= (ucNumTMU<<(21-2)) 
		+ (((FxU32)0)<<(17-2)) /*LOD0*/
		+ (FxU32 *)SST_TEX_ADDRESS(sst);
	/* write the value */
	ISET(texAddrBlank[0], Val1);
	/* set @ to second line, to use bits 32..63*/
	volatile const FxU32 *texAddrBlank2
		= (ucNumTMU<<(21-2))
		+ (((FxU32)0)<<(17-2)) /*LOD0*/
		+ (1<<(9-2))
		+ (FxU32 *)SST_TEX_ADDRESS(sst);
	/* write the value */
	ISET(texAddrBlank2[0], Val2);
}

unsigned long
CheckRead(	FxU32 * const sst,
			SstRegs * const sstregs,
			const uint32_t baseAddr,
			const char ucNumTMU,
			const unsigned char bNominal,
			const uint32_t Val1,
			const uint32_t Val2,
			const uint32_t ValOther1,
			const uint32_t ValOther2,
			def_sFaultSourceScoreRec* const pFaultSrcCtx)
{
	unsigned long NbErr=0;
	const unsigned char nBank = (baseAddr<0x200000) ? 0 : 1;
	
	const def_eFaultSource TMUTexWE 			= (ucNumTMU == 0) ? U9_TMU0_TEX_WE : U8_TMU1_TEX_WE; 
	const def_eFaultSource TMUTexCAS0 			= (ucNumTMU == 0) ? U9_TMU0_TEX_CAS0 : U8_TMU1_TEX_CAS0; 
	const def_eFaultSource TMUTexCAS1 			= (ucNumTMU == 0) ? U9_TMU0_TEX_CAS1 : U8_TMU1_TEX_CAS1; 
	const def_eFaultSource TMUTexCAS2 			= (ucNumTMU == 0) ? U9_TMU0_TEX_CAS2 : U8_TMU1_TEX_CAS2; 
	const def_eFaultSource TMUTexCAS3 			= (ucNumTMU == 0) ? U9_TMU0_TEX_CAS3 : U8_TMU1_TEX_CAS3; 
	const def_eFaultSource _TMUTexRAS0 			= (ucNumTMU == 0) ? U9_TMU0_TEX_RAS0 : U8_TMU1_TEX_RAS0; 
	const def_eFaultSource _TMUTexRAS1 			= (ucNumTMU == 0) ? U9_TMU0_TEX_RAS1 : U8_TMU1_TEX_RAS1; 
	const def_eFaultSource TMUTexRASCurrent 	= (nBank == 0) ? _TMUTexRAS0 : _TMUTexRAS1;
	const def_eFaultSource _MEMChip_B0_0_CASL	= (ucNumTMU == 0) ? U14_CASL : U13_CASL;
	const def_eFaultSource _MEMChip_B0_1_CASL	= (ucNumTMU == 0) ? U12_CASL : U11_CASL;
	const def_eFaultSource _MEMChip_B0_2_CASL	= (ucNumTMU == 0) ? U18_CASL : U16_CASL;
	const def_eFaultSource _MEMChip_B0_3_CASL	= (ucNumTMU == 0) ? U17_CASL : U15_CASL;
	const def_eFaultSource _MEMChip_B1_0_CASL	= (ucNumTMU == 0) ? U23_CASL : U27_CASL;
	const def_eFaultSource _MEMChip_B1_1_CASL	= (ucNumTMU == 0) ? U24_CASL : U28_CASL;
	const def_eFaultSource _MEMChip_B1_2_CASL	= (ucNumTMU == 0) ? U25_CASL : U29_CASL;
	const def_eFaultSource _MEMChip_B1_3_CASL	= (ucNumTMU == 0) ? U26_CASL : U30_CASL;
	const def_eFaultSource MEMChip_0_CASL		= (nBank == 0) ? _MEMChip_B0_0_CASL : _MEMChip_B1_0_CASL;
	const def_eFaultSource MEMChip_1_CASL		= (nBank == 0) ? _MEMChip_B0_1_CASL : _MEMChip_B1_1_CASL;
	const def_eFaultSource MEMChip_2_CASL		= (nBank == 0) ? _MEMChip_B0_2_CASL : _MEMChip_B1_2_CASL;
	const def_eFaultSource MEMChip_3_CASL		= (nBank == 0) ? _MEMChip_B0_3_CASL : _MEMChip_B1_3_CASL;
	
	const def_eFaultSource _MEMChip_B0_0_CASH	= (ucNumTMU == 0) ? U14_CASH : U13_CASH;
	const def_eFaultSource _MEMChip_B0_1_CASH	= (ucNumTMU == 0) ? U12_CASH : U11_CASH;
	const def_eFaultSource _MEMChip_B0_2_CASH	= (ucNumTMU == 0) ? U18_CASH : U16_CASH;
	const def_eFaultSource _MEMChip_B0_3_CASH	= (ucNumTMU == 0) ? U17_CASH : U15_CASH;
	const def_eFaultSource _MEMChip_B1_0_CASH	= (ucNumTMU == 0) ? U23_CASH : U27_CASH;
	const def_eFaultSource _MEMChip_B1_1_CASH	= (ucNumTMU == 0) ? U24_CASH : U28_CASH;
	const def_eFaultSource _MEMChip_B1_2_CASH	= (ucNumTMU == 0) ? U25_CASH : U29_CASH;
	const def_eFaultSource _MEMChip_B1_3_CASH	= (ucNumTMU == 0) ? U26_CASH : U30_CASH;
	const def_eFaultSource MEMChip_0_CASH		= (nBank == 0) ? _MEMChip_B0_0_CASH : _MEMChip_B1_0_CASH;
	const def_eFaultSource MEMChip_1_CASH		= (nBank == 0) ? _MEMChip_B0_1_CASH : _MEMChip_B1_1_CASH;
	const def_eFaultSource MEMChip_2_CASH		= (nBank == 0) ? _MEMChip_B0_2_CASH : _MEMChip_B1_2_CASH;
	const def_eFaultSource MEMChip_3_CASH		= (nBank == 0) ? _MEMChip_B0_3_CASH : _MEMChip_B1_3_CASH;

	const def_eFaultSource _MEMChip_B0_0_RAS	= (ucNumTMU == 0) ? U14_RAS : U13_RAS;
	const def_eFaultSource _MEMChip_B0_1_RAS	= (ucNumTMU == 0) ? U12_RAS : U11_RAS;
	const def_eFaultSource _MEMChip_B0_2_RAS	= (ucNumTMU == 0) ? U18_RAS : U16_RAS;
	const def_eFaultSource _MEMChip_B0_3_RAS	= (ucNumTMU == 0) ? U17_RAS : U15_RAS;
	const def_eFaultSource _MEMChip_B1_0_RAS	= (ucNumTMU == 0) ? U23_RAS : U27_RAS;
	const def_eFaultSource _MEMChip_B1_1_RAS	= (ucNumTMU == 0) ? U24_RAS : U28_RAS;
	const def_eFaultSource _MEMChip_B1_2_RAS	= (ucNumTMU == 0) ? U25_RAS : U29_RAS;
	const def_eFaultSource _MEMChip_B1_3_RAS	= (ucNumTMU == 0) ? U26_RAS : U30_RAS;
	const def_eFaultSource MEMChip_0_RAS		= (nBank == 0) ? _MEMChip_B0_0_RAS : _MEMChip_B1_0_RAS;
	const def_eFaultSource MEMChip_1_RAS		= (nBank == 0) ? _MEMChip_B0_1_RAS : _MEMChip_B1_1_RAS;
	const def_eFaultSource MEMChip_2_RAS		= (nBank == 0) ? _MEMChip_B0_2_RAS : _MEMChip_B1_2_RAS;
	const def_eFaultSource MEMChip_3_RAS		= (nBank == 0) ? _MEMChip_B0_3_RAS : _MEMChip_B1_3_RAS;

	const def_eFaultSource _MEMChip_B0_0_WE		= (ucNumTMU == 0) ? U14_WE : U13_WE;
	const def_eFaultSource _MEMChip_B0_1_WE		= (ucNumTMU == 0) ? U12_WE : U11_WE;
	const def_eFaultSource _MEMChip_B0_2_WE		= (ucNumTMU == 0) ? U18_WE : U16_WE;
	const def_eFaultSource _MEMChip_B0_3_WE		= (ucNumTMU == 0) ? U17_WE : U15_WE;
	const def_eFaultSource _MEMChip_B1_0_WE		= (ucNumTMU == 0) ? U23_WE : U27_WE;
	const def_eFaultSource _MEMChip_B1_1_WE		= (ucNumTMU == 0) ? U24_WE : U28_WE;
	const def_eFaultSource _MEMChip_B1_2_WE		= (ucNumTMU == 0) ? U25_WE : U29_WE;
	const def_eFaultSource _MEMChip_B1_3_WE		= (ucNumTMU == 0) ? U26_WE : U30_WE;
	const def_eFaultSource MEMChip_0_WE		= (nBank == 0) ? _MEMChip_B0_0_WE : _MEMChip_B1_0_WE;
	const def_eFaultSource MEMChip_1_WE		= (nBank == 0) ? _MEMChip_B0_1_WE : _MEMChip_B1_1_WE;
	const def_eFaultSource MEMChip_2_WE		= (nBank == 0) ? _MEMChip_B0_2_WE : _MEMChip_B1_2_WE;
	const def_eFaultSource MEMChip_3_WE		= (nBank == 0) ? _MEMChip_B0_3_WE : _MEMChip_B1_3_WE;

	const def_eFaultSource _RES_RAS0		= (ucNumTMU == 0) ? R118 : R115;
	const def_eFaultSource _RES_RAS1		= (ucNumTMU == 0) ? R149 : R150;
	const def_eFaultSource RES_RAS			= (nBank == 0) ? _RES_RAS0 : _RES_RAS1;
	const def_eFaultSource RES_CAS			= (ucNumTMU == 0) ? RA36 : RA32;
	const def_eFaultSource RES_WE			= (ucNumTMU == 0) ? R117 : R114;
	
	clearScreen(sstregs,0x00000000,2,2);
	/* set to mem addr */
	ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (baseAddr >> 3));
	/* draw a 2x2 square */
	drawSquare(sstregs, ucNumTMU, 0, 0, 2);
	sst1InitIdle(sst);
	
	/* first line, to use bits 00..31 */
	const uint32_t L1 = IGET(sst[(SST_LFB_ADDR>>2) + 0]);
	/* second line, to use bits 32..63 */
	const uint32_t L2 = IGET(sst[(SST_LFB_ADDR>>2) + (2048>>2) + 0]);
	
	const uint32_t ErrorMark_L1 		= (L1 ^ Val1);
	const uint32_t ErrorMark_L2 		= (L2 ^ Val2);
	
	const uint32_t ErrorMark_L1_Other	= (L1 ^ ValOther1);
	const uint32_t ErrorMark_L2_Other	= (L2 ^ ValOther2);
	
	if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 4)
	{
		NbErr++;
		
		/* If we are reading the value of the other Bank
		* then it has to be a bank select problem*/
		if(!bNominal && count_bit32(ErrorMark_L1_Other & 0x0000FFFF) < 4)
		{
			FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  MEMChip_0_RAS, 2.0);
		}
		else
		{
			/* WE can fail only in case of plain failure */
			if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 8)
			{
				/*WE are shared accross all memory chips so
				* we divide the weight by 4.*/
				FaultSource_addScore(pFaultSrcCtx,  TMUTexWE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  RES_WE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_0_WE, 1.0);
			}
			
			unsigned char bLSBFailed = false;
			unsigned char bMSBFailed = false;
			if(count_bit32(ErrorMark_L1 & 0x000000FF) > 2)
			{
				/*CAS are shared accross multiple memory chips so
				* we divide the weight by 2.*/
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS0, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+1, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_0_CASL, 1.0);
				bLSBFailed = true;
			}
			
			if(count_bit32(ErrorMark_L1 & 0x0000FF00) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS1, 1.0/2);;
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+2, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_0_CASH, 1.0);
				bMSBFailed = true;
			}
			
			/* RAS is declared failed only if both CAS failed */
			if(bLSBFailed && bMSBFailed)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_0_RAS, 4.0);
			}
		}
	}
	
	if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 4)
	{
		NbErr++;
		
		if(!bNominal && count_bit32(ErrorMark_L1_Other & 0xFFFF0000) < 4)
		{
			FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  MEMChip_1_RAS, 2.0);
		}
		else
		{
			if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 8)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexWE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  RES_WE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_1_WE, 1.0);
			}
			
			unsigned char bLSBFailed = false;
			unsigned char bMSBFailed = false;
			if(count_bit32(ErrorMark_L1 & 0x00FF0000) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS0, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+1, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_1_CASL, 1.0);
				bLSBFailed = true;
			}
			
			if(count_bit32(ErrorMark_L1 & 0xFF000000) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS1, 1.0/2);;
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+2, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_1_CASH, 1.0);
				bMSBFailed = true;
			}
			
			if(bLSBFailed && bMSBFailed)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_1_RAS, 4.0);
			}
		}
	}
	
	if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 4)
	{
		NbErr++;
		
		if(!bNominal && count_bit32(ErrorMark_L2_Other & 0x0000FFFF) < 4)
		{
			FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  MEMChip_2_RAS, 2.0);
		}
		else
		{
			if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 8)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexWE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  RES_WE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_2_WE, 1.0);
			}
			
			unsigned char bLSBFailed = false;
			unsigned char bMSBFailed = false;
			if(count_bit32(ErrorMark_L2 & 0x000000FF) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS2, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+3, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_2_CASL, 1.0);
				bLSBFailed = true;
			}
			
			if(count_bit32(ErrorMark_L2 & 0x0000FF00) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS3, 1.0/2);;
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+4, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_2_CASH, 1.0);
				bMSBFailed = true;
			}
			
			if(bLSBFailed && bMSBFailed)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_2_RAS, 4.0);
			}
		}
	}
	
	if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 4)
	{
		NbErr++;
		
		if(!bNominal && count_bit32(ErrorMark_L2_Other & 0xFFFF0000) < 4)
		{
			FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0/2);
			FaultSource_addScore(pFaultSrcCtx,  MEMChip_3_RAS, 2.0);
		}
		else
		{
			if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 8)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexWE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  RES_WE, 1.0/4);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_3_WE, 1.0);
			}
			
			unsigned char bLSBFailed = false;
			unsigned char bMSBFailed = false;
			if(count_bit32(ErrorMark_L2 & 0x00FF0000) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS2, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+3, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_3_CASL, 1.0);
				bLSBFailed = true;
			}
			
			if(count_bit32(ErrorMark_L2 & 0xFF000000) > 2)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexCAS3, 1.0/2);;
				FaultSource_addScore(pFaultSrcCtx,  RES_CAS+4, 1.0/2);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_3_CASH, 1.0);
				bMSBFailed = true;
			}
			
			if(bLSBFailed && bMSBFailed)
			{
				FaultSource_addScore(pFaultSrcCtx,  TMUTexRASCurrent, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  RES_RAS, 1.0);
				FaultSource_addScore(pFaultSrcCtx,  MEMChip_3_RAS, 4.0);
			}
		}
	}
	
	return NbErr;
}

unsigned long
TestControl(	sst1DeviceInfoStruct * const devInfo,
				FxU32 * const sst,
				SstRegs * const sstregs,
				const char ucNumTMU,
				const unsigned char RamSizeMB,
				def_sFaultSourceScoreRec * const pFaultSrcCtx)
{
	unsigned long NbErr=0;
	
	sst1InitIdle(sst);
	unsigned long _trexInit0 = IGET(SST_TREX(sstregs,ucNumTMU)->trexInit0);
	devInfo->tmuInit0[(int)ucNumTMU] = SST_TREXINIT0_DEFAULT ; 
	ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]);
	sst1InitIdle(sst);
	
	/* set downstream TMUs to passthrough */
	for (int i=0; i<ucNumTMU; i++)
		ISET(SST_TREX(sstregs,i)->textureMode, SST_TC_PASS | SST_TCA_PASS);
	
	const uint32_t TestVal1			= get_notnull_random_balanced_mByte();
	logT("TestVal1 = %08X\n",TestVal1);
	
	uint32_t TestVal2			= 0;
	do
	{
		TestVal2 = get_notnull_random_balanced_mByte();
	}
	while((count_bit32((TestVal2 ^ TestVal1)) < 12));
	logT("TestVal2 = %08X\n",TestVal2);
	
	uint32_t TestValBlank1	= 0;
	do
	{
		TestValBlank1 = get_notnull_random_balanced_mByte();
	}
	while(	(count_bit32((TestValBlank1 ^ TestVal1) & 0x0000FFFF) < 6)
		 || (count_bit32((TestValBlank1 ^ TestVal1) & 0xFFFF0000) < 6)
		 || (count_bit32((TestValBlank1 ^ TestVal2)) < 12));
	logT("TestValBlank1 = %08X\n", TestValBlank1);
		 
	uint32_t TestValBlank2	= 0;
	do
	{
		TestValBlank2 = get_notnull_random_balanced_mByte();
	}
	while(	(count_bit32((TestValBlank2 ^ TestVal2) & 0x0000FFFF) < 6)
		 || (count_bit32((TestValBlank2 ^ TestVal2) & 0xFFFF0000) < 6)
		 || (count_bit32((TestValBlank2 ^ TestValBlank1)) < 12)
		 || (count_bit32((TestValBlank2 ^ TestVal1)) < 12));
	logT("TestValBlank2 = %08X\n", TestValBlank2);
	
	/* write initial Values */
	/* Bank 0*/
	WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestValBlank1, TestValBlank2);
	/* Bank 1*/
	if(RamSizeMB>2)
	{
		WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestValBlank1, TestValBlank2);
	}
	
	/* write to Bank 0 */
	WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestVal1, TestVal2);

	/* read and check Bank 0 (nominal check)*/
	NbErr += CheckRead(sst, sstregs, 0x000000, ucNumTMU,
						true, TestVal1, TestVal2, TestValBlank1, TestValBlank2, pFaultSrcCtx);
	/* if Bank 1 available*/
	if(RamSizeMB>2)
	{
		/* read and check Bank 1(no modification check)*/
		NbErr += CheckRead(sst, sstregs, 0x200000, ucNumTMU,
							false, TestValBlank1, TestValBlank2, TestVal1, TestVal2,  pFaultSrcCtx);

		/* write initial Values */
		/* Bank 0*/
		WriteTex(sst, sstregs, 0x000000, ucNumTMU, TestValBlank1, TestValBlank2);
		/* Bank 1*/
		if(RamSizeMB>2)
		{
			WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestValBlank1, TestValBlank2);
		}
		
		/* write to Bank 1 */
		WriteTex(sst, sstregs, 0x200000, ucNumTMU, TestVal1, TestVal2);
		
		/* read and check Bank 1 (nominal check)*/
		NbErr += CheckRead(sst, sstregs, 0x200000, ucNumTMU,
							true, TestVal1, TestVal2, TestValBlank1, TestValBlank2, pFaultSrcCtx);
		
		/* read and check Bank 0 (no modification check)*/
		NbErr += CheckRead(sst, sstregs, 0x000000, ucNumTMU,
							false, TestValBlank1, TestValBlank2, TestVal1, TestVal2,  pFaultSrcCtx);
	}
	
	clearScreen(sstregs,0x00000000,2,2);
	
	sst1InitIdle(sst);
	devInfo->tmuInit0[(int)ucNumTMU] = _trexInit0;
	ISET(SST_TREX(sst,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]);
	sst1InitIdle(sst);
	
	return NbErr;
}