new cpuid copied from H5
This commit is contained in:
koolsmoky
337
glide3x/cvg/glide3/src/cpuid.c
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337
glide3x/cvg/glide3/src/cpuid.c
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@@ -0,0 +1,337 @@
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/*
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* CPU detection code
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*
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* $Header$
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* $Log$
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* Revision 1.1.2.10 2004/10/05 14:54:29 dborca
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* DOS/OpenWatcom woes
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*
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* Revision 1.1.2.9 2003/08/04 12:45:47 dborca
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* Preparing for MinGW 2.0
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*
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* Revision 1.1.2.8 2003/07/29 10:04:32 dborca
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* Shamelessness.
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* Safeguard in CPUID.
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* Changed contact address!
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* Koolsmoky's texture download fixes.
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*
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* Revision 1.1.2.7 2003/07/25 07:14:58 dborca
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* ... in the name of the Linux, DRI and the sacred Glide...
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*
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* Revision 1.1.2.6 2003/07/24 13:13:03 koolsmoky
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* use __try/__except mechanism for win32 to catch SSE sigillegal in win95
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*
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* Revision 1.1.2.5 2003/07/01 11:16:42 dborca
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* fixed a bug in GNUC code when running Intel; also removed detritus
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*
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* Revision 1.1.2.3 2003/06/13 07:22:58 dborca
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* more fixes to NASM sources
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*
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*/
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#include <signal.h>
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#include <setjmp.h>
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#include <string.h>
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#include "cpuid.h"
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typedef unsigned long word32;
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/* These are the bit flags that get set on calling cpuid
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* with register eax set to 1
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*/
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#define _MMX_FEATURE_BIT 0x00800000
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#define _SSE_FEATURE_BIT 0x02000000
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#define _SSE2_FEATURE_BIT 0x04000000
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/* This bit is set when cpuid is called with
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* register set to 80000001h (only applicable to AMD)
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*/
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#define _3DNOW_FEATURE_BIT 0x80000000
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#define _3DNOWPLUS_FEATURE_BIT 0x40000000
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#define _MMXPLUS_FEATURE_BIT 0x00400000
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/* Testing code:
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* TEST_SSE = xorps xmm0, xmm0
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* TEST_SSE2 = xorpd xmm0, xmm0
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* TEST_3DNOW = femms
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* TEST_MMX = emms
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* TEST_3DNOWPLUS = femms | pswapd mm0, mm0 | femms
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* TEST_MMXPLUS = emms | pminsw mm0, mm0 | emms
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*/
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#ifdef __GNUC__
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#define TEST_CPUID(f) __asm __volatile ("cpuid"::"a"(f):"%ebx", "%ecx", "%edx")
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#define TEST_SSE() __asm __volatile (".byte 0x0f, 0x57, 0xc0")
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#define TEST_SSE2() __asm __volatile (".byte 0x66, 0x0f, 0x57, 0xc0")
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#define TEST_3DNOW() __asm __volatile (".byte 0x0f, 0x0e")
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#define TEST_MMX() __asm __volatile (".byte 0x0f, 0x77")
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#define TEST_3DNOWPLUS() __asm __volatile (".byte 0x0f, 0x0e, 0x0f, 0x0f, 0xc0, 0xbb, 0x0f, 0x0e")
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#define TEST_MMXPLUS() __asm __volatile (".byte 0x0f, 0x77, 0x0f, 0xea, 0xc0, 0x0f, 0x77")
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#else
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#define TEST_CPUID(f) __asm { _asm mov eax, f _asm cpuid }
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#define TEST_SSE() __asm { _asm _emit 0x0f _asm _emit 0x57 _asm _emit 0xc0 }
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#define TEST_SSE2() __asm { _asm _emit 0x66 _asm _emit 0x0f _asm _emit 0x57 _asm _emit 0xc0 }
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#define TEST_3DNOW() __asm { _asm _emit 0x0f _asm _emit 0x0e }
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#define TEST_MMX() __asm { _asm _emit 0x0f _asm _emit 0x77 }
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#define TEST_3DNOWPLUS() __asm { _asm _emit 0x0f _asm _emit 0x0e _asm _emit 0x0f _asm _emit 0x0f _asm _emit 0xc0 _asm _emit 0xbb _asm _emit 0x0f _asm _emit 0x0e }
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#define TEST_MMXPLUS() __asm { _asm _emit 0x0f _asm _emit 0x77 _asm _emit 0x0f _asm _emit 0xea _asm _emit 0xc0 _asm _emit 0x0f _asm _emit 0x77 }
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#endif
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#ifndef __MSC__
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static jmp_buf j;
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/* Desc: signal handler
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*
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* In : signal number
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* Out : -
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*
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* Note: returns by `longjmp'ing
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*/
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static void handler (int signal)
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{
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longjmp(j, signal + 1); /* so we can tell... also ensure we don't pass 0 */
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}
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/* Desc: check if CPU has specific feature
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*
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* In : feature request
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* Out : 0 == fail, input == pass
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*
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* Note: this should be in the `has_feature' body. The reason it isn't:
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* under some systems (notably Linux), the `setjmp' may thrash EBX,
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* which is used for PositionIndependentCode/GlobalOffsetTable system.
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* Since EBX is non-volatile register, it should be restored upon return.
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*/
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static int check_feature (int feature)
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{
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if (setjmp(j)) {
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/* we got here only when `longjmp'ed by signal handlers */
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return 0;
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} else {
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/* we have signals and jump buffer set */
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switch (feature) {
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case _CPU_HAS_CPUID: TEST_CPUID(0); break;
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case _CPU_FEATURE_SSE: TEST_SSE(); break;
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case _CPU_FEATURE_SSE2: TEST_SSE2(); break;
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case _CPU_FEATURE_3DNOW: TEST_3DNOW(); break;
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case _CPU_FEATURE_MMX: TEST_MMX(); break;
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case _CPU_FEATURE_3DNOWPLUS: TEST_3DNOWPLUS(); break;
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case _CPU_FEATURE_MMXPLUS: TEST_MMXPLUS(); break;
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default: return 0;
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}
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return feature;
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}
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}
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#endif
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/* Desc: perform (possibly faulting) instructions in a safe manner
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*
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* In : feature request
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* Out : 0 == fail, input == pass
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*
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* Note: pure ANSI code; stupid Watcom cannot handle this.
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*/
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static int has_feature (int feature)
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{
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#ifndef __MSC__
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int rv;
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/* register signal handlers */
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void (*old_sigill)(int) = signal(SIGILL, handler);
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if (old_sigill == SIG_ERR) {
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return 0;
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}
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rv = check_feature(feature);
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/* restore the signal handlers */
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signal(SIGILL, old_sigill);
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return rv;
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#else
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/* Use the non-standard __try/__except mechanism because win95 fails to catch
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* sigillegal for SSE using standard signal mechanism.
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* HACK ALERT! HACK ALERT! HACK ALERT!
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* This means the MinGW version cannot be safely run under Win95!
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*/
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#define _TRY() __try {
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#define _EXCEPTION() } __except(1) { return 0; } /* EXCEPTION_EXECUTE_HANDLER=1 */
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switch (feature) {
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case _CPU_HAS_CPUID: _TRY() TEST_CPUID(0) _EXCEPTION() break;
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case _CPU_FEATURE_SSE: _TRY() TEST_SSE() _EXCEPTION() break;
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case _CPU_FEATURE_SSE2: _TRY() TEST_SSE2() _EXCEPTION() break;
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case _CPU_FEATURE_3DNOW: _TRY() TEST_3DNOW() _EXCEPTION() break;
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case _CPU_FEATURE_MMX: _TRY() TEST_MMX() _EXCEPTION() break;
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case _CPU_FEATURE_3DNOWPLUS: _TRY() TEST_3DNOWPLUS() _EXCEPTION() break;
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case _CPU_FEATURE_MMXPLUS: _TRY() TEST_MMXPLUS() _EXCEPTION() break;
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default: return 0;
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}
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return feature;
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#endif
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}
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/* Desc: get CPU info
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*
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* In : pointer to _p_info
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* Out : features
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*
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* Note: -
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*/
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int _cpuid (_p_info *pinfo)
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{
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word32 dwId = 0;
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word32 dwFeature = 0;
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word32 dwExt = 0;
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int feature = 0, os_support = 0;
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char Ident[13];
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if (!has_feature(_CPU_HAS_CPUID)) {
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return 0;
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}
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#ifdef __GNUC__
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__asm("\n\
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pushl %%ebx \n\
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/* get the vendor string */ \n\
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xorl %%eax, %%eax \n\
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cpuid \n\
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movl %%ebx, %3 \n\
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movl %%edx, %4 \n\
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movl %%ecx, %5 \n\
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/* get the Standard bits */ \n\
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movl $1, %%eax \n\
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cpuid \n\
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movl %%eax, %1 \n\
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movl %%edx, %2 \n\
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/* get AMD-specials */ \n\
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movl $0x80000000, %%eax \n\
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cpuid \n\
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cmpl $0x80000000, %%eax \n\
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jc 0f \n\
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movl $0x80000001, %%eax \n\
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cpuid \n\
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movl %%edx, %0 \n\
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0: \n\
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popl %%ebx \n\
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":"=g"(dwExt), "=g"(dwId), "=g"(dwFeature),
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"=g"(((long *)Ident)[0]), "=g"(((long *)Ident)[1]), "=g"(((long *)Ident)[2])
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::"%eax", "%ebx", "%ecx", "%edx");
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#else
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_asm
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{
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push ebx
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push ecx
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push edx
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/* get the vendor string */
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xor eax,eax
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cpuid
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mov dword ptr [Ident],ebx
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mov dword ptr [Ident+4],edx
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mov dword ptr [Ident+8],ecx
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/* get the Standard bits */
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mov eax,1
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cpuid
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mov dwId,eax
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mov dwFeature,edx
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/* get AMD-specials */
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mov eax,80000000h
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cpuid
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cmp eax,80000000h
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jc notamd
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mov eax,80000001h
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cpuid
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mov dwExt,edx
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notamd:
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pop ecx
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pop ebx
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pop edx
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}
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#endif
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#ifndef __WATCOMC__
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/* stupid watcom does not sigill... */
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if (dwFeature & _MMX_FEATURE_BIT) {
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feature |= _CPU_FEATURE_MMX;
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os_support |= has_feature(_CPU_FEATURE_MMX);
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}
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if (dwExt & _3DNOW_FEATURE_BIT) {
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feature |= _CPU_FEATURE_3DNOW;
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os_support |= has_feature(_CPU_FEATURE_3DNOW);
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}
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if (dwExt & _3DNOWPLUS_FEATURE_BIT) {
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feature |= _CPU_FEATURE_3DNOWPLUS;
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os_support |= has_feature(_CPU_FEATURE_3DNOWPLUS);
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}
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if (dwExt & _MMXPLUS_FEATURE_BIT) {
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feature |= _CPU_FEATURE_MMXPLUS;
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os_support |= has_feature(_CPU_FEATURE_MMXPLUS);
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}
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if (dwFeature & _SSE_FEATURE_BIT) {
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feature |= _CPU_FEATURE_SSE;
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os_support |= has_feature(_CPU_FEATURE_SSE);
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}
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if (dwFeature & _SSE2_FEATURE_BIT) {
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feature |= _CPU_FEATURE_SSE2;
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os_support |= has_feature(_CPU_FEATURE_SSE2);
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}
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#endif
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if (pinfo) {
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memset(pinfo, 0, sizeof(_p_info));
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pinfo->os_support = os_support;
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pinfo->feature = feature;
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pinfo->family = (dwId >> 8) & 0xF; /* retrieving family */
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pinfo->model = (dwId >> 4) & 0xF; /* retrieving model */
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pinfo->stepping = dwId & 0xF; /* retrieving stepping */
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Ident[12] = 0;
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strcpy(pinfo->v_name, Ident);
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}
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return feature;
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}
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#if CPUTEST
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#include <stdio.h>
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/* Desc:
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*
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* In :
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* Out :
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*
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* Note:
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*/
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int main (void)
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{
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_p_info p;
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_cpuid(&p);
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printf("vendor : %s\n", p.v_name);
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printf("family : %d\n", p.family);
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printf("model : %d\n", p.model);
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printf("stepping: %X\n", p.stepping);
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printf("feature : %08x\n", p.feature);
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printf("support : %08x\n", p.os_support);
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printf("--------\n");
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printf("cpuid : %d\n", has_feature(_CPU_HAS_CPUID));
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printf("MMX : %d\n", has_feature(_CPU_FEATURE_MMX));
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printf("SSE : %d\n", has_feature(_CPU_FEATURE_SSE));
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printf("SSE2 : %d\n", has_feature(_CPU_FEATURE_SSE2));
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printf("3DNow! : %d\n", has_feature(_CPU_FEATURE_3DNOW));
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printf("3DNow!+ : %d\n", has_feature(_CPU_FEATURE_3DNOWPLUS));
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printf("MMX+ : %d\n", has_feature(_CPU_FEATURE_MMXPLUS));
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return 0;
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}
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#endif
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23
glide3x/cvg/incsrc/cpuid.h
Normal file
23
glide3x/cvg/incsrc/cpuid.h
Normal file
@@ -0,0 +1,23 @@
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#ifndef CPUID_H_included
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#define CPUID_H_included
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#define _CPU_HAS_CPUID 0xffff
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#define _CPU_FEATURE_MMX 0x0001
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#define _CPU_FEATURE_SSE 0x0002
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#define _CPU_FEATURE_SSE2 0x0004
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#define _CPU_FEATURE_3DNOW 0x0008
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#define _CPU_FEATURE_3DNOWPLUS 0x0010
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#define _CPU_FEATURE_MMXPLUS 0x0020
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typedef struct _processor_info {
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char v_name[13]; /* vendor name */
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int family; /* family of the processor, eg. Intel_Pentium_Pro is family 6 processor */
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int model; /* madel of processor, eg. Intel_Pentium_Pro is model 1 of family 6 processor */
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int stepping; /* Processor revision number */
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int feature; /* processor Feature (same as return value). */
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int os_support; /* does OS Support the feature */
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} _p_info;
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int _cpuid (_p_info *);
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#endif
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