texture base address alignment fix for dxt1 downloads.
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@@ -1600,6 +1600,10 @@ _grTexTextureMemRequired( GrLOD_t small_lod, GrLOD_t large_lod,
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switch(format) {
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case GR_TEXFMT_ARGB_CMP_FXT1:
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case GR_TEXFMT_ARGB_CMP_DXT1: /* HACK: align texture base address for
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* the smallest mipmap.
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* See grTexDownloadMipMapLevelPartial.
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*/
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/* In this case, do not mirror the aspect ratios, as the minimum
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* size of a mipmap level is 8x4, so the tables are not symmetric
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* w.r.t. sign of the aspect ratio, so keep the sign. */
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@@ -1622,7 +1626,6 @@ _grTexTextureMemRequired( GrLOD_t small_lod, GrLOD_t large_lod,
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}
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break;
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case GR_TEXFMT_ARGB_CMP_DXT1:
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case GR_TEXFMT_ARGB_CMP_DXT2:
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case GR_TEXFMT_ARGB_CMP_DXT3:
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case GR_TEXFMT_ARGB_CMP_DXT4:
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@@ -1715,6 +1718,9 @@ _grTexCalcBaseAddress( FxU32 start, GrLOD_t large_lod,
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switch(format) {
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case GR_TEXFMT_ARGB_CMP_FXT1:
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case GR_TEXFMT_ARGB_CMP_DXT1: /* HACK: compensate for the hack to align the
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* base address in _grTexTextureMemRequired.
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*/
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/* FXT1 format: Don't mirror the aspect ratios, because of the 8x4 limit */
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if ( odd_even_mask == GR_MIPMAPLEVELMASK_BOTH ) {
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sum_of_lod_sizes = _grMipMapOffsetCmp4Bit[aspect]
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@@ -1731,7 +1737,6 @@ _grTexCalcBaseAddress( FxU32 start, GrLOD_t large_lod,
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}
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break;
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case GR_TEXFMT_ARGB_CMP_DXT1:
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case GR_TEXFMT_ARGB_CMP_DXT2:
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case GR_TEXFMT_ARGB_CMP_DXT3:
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case GR_TEXFMT_ARGB_CMP_DXT4:
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@@ -1133,12 +1133,16 @@ _grTexDownloadMipMapLevelPartialTiled(GrChipID_t tmu,
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case 4:
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{
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texOffset += (t * texStrideBytes);
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for(; t <= maxT; t+=2) {
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LINEAR_WRITE_BEGIN(1, SSTCP_PKT5_LFB, texOffset, 0x0UL, 0x0UL);
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LINEAR_WRITE_SET(texOffset, *src32);
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for(; t <= maxT; t+=4) {
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FxI32 s;
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LINEAR_WRITE_BEGIN(2, SSTCP_PKT5_LFB, texOffset, 0x00UL, 0x00UL);
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for (s = 0; s < 2; s++) {
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LINEAR_WRITE_SET(texOffset, *src32);
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src32++;
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texOffset += texStrideBytes;
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}
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LINEAR_WRITE_END();
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src32++;
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texOffset += texStrideBytes;
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}
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}
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break;
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@@ -1506,12 +1510,10 @@ GR_ENTRY(grTexDownloadMipMapLevelPartial,
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* 16 bytes (4x4x1) which also matches the alignment
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* restriction.
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*/
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/* XXX: we can't skip this part for DXT1 because the smallest
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* mipmap is 8 bytes (4x4x1/2).
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/* Note: we skip this part for DXT1 and use the hack
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* in _grTexTextureMemRequired to align the baseAddr.
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*/
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if(format != GR_TEXFMT_ARGB_CMP_FXT1 &&
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format != GR_TEXFMT_ARGB_CMP_DXT2 && format != GR_TEXFMT_ARGB_CMP_DXT3 &&
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format != GR_TEXFMT_ARGB_CMP_DXT4 && format != GR_TEXFMT_ARGB_CMP_DXT5 ) {
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if(format != GR_TEXFMT_ARGB_CMP_FXT1 && format < GR_TEXFMT_ARGB_CMP_DXT1 ) {
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const FxU32
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aspectIndex = ((aspectRatio < GR_ASPECT_LOG2_1x1)
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? -aspectRatio
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@@ -1520,9 +1522,7 @@ GR_ENTRY(grTexDownloadMipMapLevelPartial,
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? GR_LOD_LOG2_256 : thisLod + 1),
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formatMult = _grBitsPerTexel[format];
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FxU32
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levelSize = ((format == GR_TEXFMT_ARGB_CMP_DXT1)
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? (_grMipMapHostSizeDXT[aspectIndex][lodIndex] * formatMult) >> 3
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: (_grMipMapHostSize[aspectIndex][lodIndex] * formatMult) >> 3); /* bytes */
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levelSize = (_grMipMapHostSize[aspectIndex][lodIndex] * formatMult) >> 3; /* bytes */
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GR_CHECK_F(FN_NAME, formatMult == 0, "invalid texture format");
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@@ -1541,9 +1541,7 @@ GR_ENTRY(grTexDownloadMipMapLevelPartial,
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* colon.
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*/
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while(maxLod < GR_LOD_LOG2_256) {
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levelSize = ((format == GR_TEXFMT_ARGB_CMP_DXT1)
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? (_grMipMapHostSizeDXT[aspectIndex][maxLod] * formatMult) >> 3
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: (_grMipMapHostSize[aspectIndex][maxLod] * formatMult) >> 3); /* bytes */
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levelSize = (_grMipMapHostSize[aspectIndex][maxLod] * formatMult) >> 3; /* bytes */
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if (levelSize >= SST_TEXTURE_ALIGN) break;
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// check on the Even/Odd mask to see if the mip-map affects this TMU
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if((maxLod & 1) ? (evenOdd & GR_MIPMAPLEVELMASK_ODD) : (evenOdd & GR_MIPMAPLEVELMASK_EVEN))
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@@ -1588,7 +1586,7 @@ GR_ENTRY(grTexDownloadMipMapLevelPartial,
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FxU32
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width, formatSel, widthSel, max_s;
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/*
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/*
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* Interpretations:
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* formatSel: Chooses among 4, 8, 16, and 32-bit download procedures.
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* We want formatSel == log2(bitsPerTexel >> 2).
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@@ -1641,9 +1639,8 @@ GR_ENTRY(grTexDownloadMipMapLevelPartial,
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break;
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}
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if (max_s <= 0) max_s = 1;
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if (widthSel > 3) widthSel = 4;
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else if (widthSel <= 0) widthSel = 0;
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if (max_s < 1) max_s = 1;
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if (widthSel > 4) widthSel = 4;
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gc->stats.texBytes += max_s * (max_t - t + 1) * 4;
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@@ -97,15 +97,18 @@ _grTexDownload_Default_4_4(struct GrGC_s* gc, const FxU32 tmuBaseAddr,
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FxI32
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t = minT;
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for (; t <= maxT; t+=2) {
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FxU32 tex_address = tmuBaseAddr + (t << 1UL);
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const FxU32 t0 = *src32;
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LINEAR_WRITE_BEGIN(1, PACKET5_MODE, (FxU32)tex_address, 0x00UL, 0x00UL);
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LINEAR_WRITE_SET(tex_address, t0);
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for (; t <= maxT; t+=4) {
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FxU32 tex_address = tmuBaseAddr + (t << 2UL);
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FxI32 s;
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LINEAR_WRITE_BEGIN(2, PACKET5_MODE, (FxU32)tex_address, 0x00UL, 0x00UL);
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for (s = 0; s < 2; s++) {
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const FxU32 t0 = *src32;
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LINEAR_WRITE_SET(tex_address, t0);
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tex_address++;
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src32++;
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}
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LINEAR_WRITE_END();
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tex_address++;
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src32++;
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}
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#undef FN_NAME
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}
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