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add missing Rush files to glide2x side.

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This commit is contained in:
sezero
2018-08-04 11:03:15 +03:00
parent 1a273ba12a
commit 486276471e
3 changed files with 2637 additions and 0 deletions
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1658
glide2x/sst1/init/init96/initat3d.c Normal file
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glide2x/sst1/init/init96/physical.h Normal file
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/////////////////////////////////////////////////////////////////////////////
//
// PHYSICAL.H
//
// This module ...
//
// Copyright 1994-1996 Alliance Semiconductor Corporation
//
/////////////////////////////////////////////////////////////////////////////
#include "prefresh.h" /* include refresh structures */
#ifdef VG96
#define DYNAMIC_MCLK TRUE /* Set Mclk based on Puma On/Off State */
#endif
#pragma pack(1)
#undef DCI
#define DCI TRUE
#undef DIRECT_DRAW
#define DIRECT_DRAW TRUE
#undef HWSWITCH
#define HWSWITCH TRUE /* can switch HW on/off thru escap */
#define PMREGISTRY FALSE /* Read driver switches from registry. */
enum {
CHIP_3210 = 0x3210,
CHIP_6422 = 0x6422,
CHIP_6412 = 0x6412,
CHIP_AT24 = 0x6424,
CHIP_AT3D = 0x643D
};
#define MC_BETTER_HALF 0x080
#define VC_ENABLE 0x0001
#define VC_DISABLE 0x0000
#define VCPD_8BPP 0x0004
#define VCPD_15BPP 0x0008
#define VCPD_16BPP 0x000A
#define VCPD_32BPP 0x000E
#define VCWF_INDEXED 0x0000
#define VCWF_RGB 0x0020
#define VCWF_YUY2 0x0030
#define VCWF_UYVY 0x0040
#define VCWF_YYVU 0x0050
#define VCWF_YVYU 0x0060
#define VCWF_Y 0x0070
#define VC_YUV_RGB 0x0100
#define VC_STRETCH 0x0200
#define VC_INTERP 0x0400
#define VC_NOFLICKER 0x0800
#define VC2_HOR_INTERP 0x0400
#define VC2_VER_INTERP 0x0800
#define VC2_FILTER 0x1000
#define TILE_RIGHTMOST 0x10
#define N_OVERLAYS_VERS1 1
#define N_OVERLAYS_VERS2 2
#define MAX_TILES 12
typedef struct _VIDWINDOW_V1{
FxU16 VidControl;
FxU16 VidDataWidth;
FxU16 VidDataOffset;
FxU16 VidLeft;
FxU16 VidTop;
FxU16 VidRight;
FxU16 VidBottom;
FxU32 VidDataLocation;
FxU32 VidChromaKey;
FxU16 VidStretchHorz1;
short VidStretchHorz2;
FxU16 VidStretchVert1;
short VidStretchVert2;
} VIDWINDOW_V1;
typedef struct _VIDWINDOW_V2{
FxU16 VidControl; /* 0x82 */
FxU16 VidDataOffset; /* 0x84 */
FxU16 VidScaleFactorHor; /* 0x86 */
FxU16 VidScaleOffsetHor; /* 0x88 */
FxU16 VidScaleFactorVer; /* 0x8a */
FxU16 VidScaleOffsetVer; /* 0x8c */
FxU16 TileSequenceControl; /* 0x8e */
FxU16 VidChromakeyColor;
} VIDWINDOW_V2;
typedef struct _VIDWINDOWV2_SET{
VIDWINDOW_V2 VidWindowV2Set[N_OVERLAYS_VERS2];
} VIDWINDOWV2_SET;
typedef struct _TILEREGS{
FxU16 Control; /* 0x200 */
FxU16 DisplayPositionLeft; /* 0x202 */
FxU16 DisplayPositionRight; /* 0x204 */
FxU16 DisplayPositionBottom; /* 0x208 */
FxU16 DataWidth; /* 0x20a */
FxU16 DataLocationLo; /* 0x20c */
FxU8 DataLocationHi; /* 0x20e */
char Reserved[3];
} TILEREGS;
typedef struct {
char spare0_2F[0x30]; /* 0x0 */
FxU8 CLIP_CTRL; /* 0x30 */
char spare31_3F[0xF]; /* 0x31 */
FxU32 BLT_CTRL; /* 0x40 */
FxU8 spare44_45[0x2]; /* 0x44 */
FxU8 BLT_ROP; /* 0x46 */
FxU8 FxU8_MASK; /* 0x47 */
FxU8 PATTERN_REG[0x8]; /* 0x48 */
FxU32 SRC; /* 0x50 */
FxU32 DEST; /* 0x54 */
FxU32 DIM; /* 0x58 */
union{
FxU32 ROW_PITCHES;
struct{
FxU16 DEST_ROW_PITCH;
FxU16 SRC_ROW_PITCH;
};
}; /* 0x5c */
FxU32 FG_CLR; /* 0x60 */
FxU32 BG_CLR; /* 0x64 */
FxU8 spare68_70[0x70-0x68]; /* 0x68 */
FxU16 DDA_AXIAL; /* 0x70 */
FxU16 DDA_DIAGONAL; /* 0x72 */
FxU16 DDA_ERROR; /* 0x74 */
FxU8 spare76_80[0x80-0x76]; /* 0x76 */
FxU8 SerialControl; /* 0x80 */
FxU8 spare_1; /* 0x81 */
union { /* 0x82 */
VIDWINDOW_V1 V1;
VIDWINDOWV2_SET V2;
};
char spareC4_A2[0xC4-0xA2];
FxU16 MemConfig; /* 0xC4-5 */
FxU8 DACControl; /* 0xc6 */
char spare_c7; /* 0xc7 */
FxU16 VGAOverride; /* 0xC8-9 */
FxU8 PinInterface; /* 0xCA */
char spareCB; /* 0xcb */
FxU8 FeatureCnctrDisable; /* 0xcc */
FxU8 GenFeatureCnctrCtl; /* 0xcd */
FxU32 spareCE_D1; /* 0xce,0xcf,0xd0,0xd1 */
FxU8 InterlaceControl; /* 0xD2 */
FxU8 Spare3b; /* 0xd3 */
FxU8 HiReqMiss; /* 0xD4 */
FxU8 HiReqNoMiss; /* 0xd5 */
FxU8 LoReq; /* 0xd6 */
FxU8 Spare3a; /* 0xd7 */
FxU8 ExternalClock; /* 0xD8 */
FxU8 ExternalSignalTiming; /* 0xd9 */
FxU8 CommandFifoControl; /* 0xda */
FxU8 ExtendedMemoryEnable; /* 0xDB */
FxU16 BiEndianControl; /* 0xdc,0xdd */
FxU8 DE; /* 0xde */
FxU8 DF; /* 0xdf */
FxU8 RamdacControl; /* 0xe0 */
FxU8 E1; /* 0xe1 */
FxU8 E2; /* 0xe2 */
FxU8 E3; /* 0x33 */
FxU8 DACControl2; /* 0x34 */
FxU8 OverdriveRed; /* 0xE5 */
FxU8 OverdriveGreen; /* 0xE6 */
FxU8 OverdriveBlue; /* 0xE7 */
FxU8 MCLK_Ctrl; /* 0xe8 */
FxU8 MCLK_M; /* 0xe9 */
FxU8 MCLK_N; /* 0xea */
/* config register for MCLK control by HW straps, does not affect
clock directly. No longer used. */
FxU8 MCLK_SpeedSel; /* 0xeb */
FxU8 VCLK_Ctrl; /* 0xec */
FxU8 VCLK_M; /* 0xed */
FxU8 VCLK_N; /* 0xee */
char spare4a; /* 0xef */
FxU32 ScratchReg; /* 0xf0, 0xf1, 0xf2, 0xf3 */
char spare5[0x110 - 0xF4];
FxU8 UMAControl;
FxU8 UMASpare;
FxU8 UMASlaveRequest;
FxU8 UMASlaveGrant;
char spare5a[0x141 - 0x114];
FxU8 CursColor1;
FxU8 CursColor2;
char spare8[0x190 - 0x143];
FxU32 BaseAddress;
char spare6[0x1F0 - 0x194];
FxU8 GPIOControl; /* 0x1f0 */
FxU8 GPIODirection; /* 0x1f1 */
FxU8 GPIOLevel; /* 0x1f2 */
FxU8 GPIOReadback; /* 0x1f3 */
FxU16 SerialInput; /* 0x1f4 */
char spare6a[0x1FA - 0x1F6];
FxU16 CurrentVerticalPosition; /* 0x1fa */
union{
FxU32 Extended_Status;
FxU8 cFIFOEntries;
}; /* 0x1fc */
TILEREGS TileRegsSet[MAX_TILES]; /* 0x200 */
char tiles_spare[0x300 - ( MAX_TILES*sizeof(TILEREGS) + 0x200) ];
/* 3D registers */
FxU32 PolygonEngineControl; /* 0x300 */
FxU32 PolygonEngineControl2; /* for HW debug */
FxU32 TextureMapBaseAddress;
FxU16 TextureFormat;
FxU8 TexelIndexOffset;
FxU8 TextureMipmapSwitch;
FxU32 _3d_register_index;
FxU32 _3d_register_data;
FxU32 Zbuffer_base_pointer;
FxU16 Zbuffer_front_clipping_plane;
FxU16 Zbuffer_back_clipping_plane;
FxU32 TexelTransparencyColor;
FxU32 FogColor;
FxU32 BackBufferBaseAddress;
char _3d_spare2[0x330-0x32C];
union{
struct {
FxU16 ClipLeft_3D;
FxU16 ClipTop_3D;
};
FxU32 ClipLeftTop_3D;
};
union{
struct {
FxU16 ClipRight_3D;
FxU16 ClipBottom_3D;
};
FxU32 ClipRightBottom_3D;
};
char _3d_spare3[0x340-0x338];
FxU32 Vertex_X;
FxU32 Vertex_Y;
FxU32 Vertex_Z;
union{
FxU32 Vertex_W;
struct{
FxU8 PadW1;
FxU8 Vertex_Red;
FxU16 PadW2;
};
};
FxU8 Vertex_L;
char _3d_spare5[0x353-0x351];
FxU8 Vertex_Alpha;
FxU8 Vertex_F;
char _3d_spare6[0x358-0x355];
union{
FxU32 Vertex_U;
struct{
FxU16 PadU1;
FxU8 Vertex_Green;
FxU8 PadU2;
};
};
union{
FxU32 Vertex_V;
struct{
FxU16 PadV1;
FxU8 Vertex_Blue;
FxU8 PadV2;
};
};
char spare360_3C0[0x3C0 - 0x360];
union{
FxU32 UFactorOffset;
struct{
FxU16 UFactor;
FxU16 UOffset;
};
};
union{
FxU32 VFactorOffset;
struct{
FxU16 VFactor;
FxU16 VOffset;
};
};
char GradReinterpCount;
char spare9[0x1000 - 0x3C9];
FxU32 BltPort;
} COP;
typedef volatile COP *LPCOP;
#define CC_INDEX 0x3d4
#define CC_DATA 0x3d5
enum{
CC_HTOTAL,
CC_HDISP_END,
CC_HBLANK_START,
CC_HBLANK_END,
CC_HSYNC_START,
CC_HSYNC_END,
CC_VTOTAL,
CC_VOVERFLOW,
CC_MAX_SCANLINE = 9,
CC_SERIAL_START_MSB = 0xC,
CC_SERIAL_START_LSB = 0xD,
CC_VSYNC_START = 0x10,
CC_VSYNC_END,
CC_VDISP_END,
CC_VBLANK_START = 0x15,
CC_VBLANK_END,
CC_GXX_VOVERFLOW = 0x1A,
CC_GXX_SERIAL_OVERFLOW = 0x1C,
CC_GXX_EXT_CRTC_CTRL = 0x1E
};
/* VGA Sequencer register defines */
#define SC_INDEX 0x3c4
#define SC_DATA 0x3c5
enum{
SC_RESET,
SC_CLOCKING_MODE,
SC_MAP_MASK,
SC_CHAR_MAP,
SC_MEM_MODE
};
#define SC_REMAP_CTRL 0x1B
#define VCLK_CTRL_MASK 3
#define VGA_SEQUENCER_SCREEN_OFF 0x20
#define MISC_OUTPUTW 0x3c2
#define MISC_OUTPUTR 0x3cc
#define PCI_BUS 1
#define DAC_ATT_8 00h
#define DAC_ATT_16 81h
#define DAC_SIERRA 02h
/* New Promotion - specific defines */
#define CLIP_ENABLE 0x1
#define INPUT_STATUS_0 0x3C2
#define INPUT_STATUS_1 0x3DA
#define VERTICAL_RETRACE_ACTIVE 0x08
#define DISPLAY_INACTIVE 0x01
#define EXT_STATUS_DWG_FIFO_ENTRIES 0x0000000F
#define ST_IN_BLT 0x00000100
#define EXT_STATUS_DWG_ENG_BUSY 0x00000400
#define EXT_STATUS_3D_ENG_BUSY 0x00800000
#define ENOUGH_FIFO_SPACE_FOR_BLIT 0x4
#define PM_SCRATCH_SPACE 20*1024
/* Graphics Engine Command reg. defines. */
#define GE_BLT_SS 0x000000001
#define GE_BLT_RECT 0x000000002
#define GE_BLT_STRIP 0x000000004
#define GE_BLT_MS 0x000000008
#define GE_BLT_SM 0x000000009
#define GE_BLT_LINE 0x00000000C
#define GE_BLT_LINE_NOEND 0x00000000D
#define GE_BLT_DIR_L 0x000000040
#define GE_BLT_DIR_U 0x000000080
#define GE_BLT_DIR_LU (GE_BLT_DIR_L + GE_BLT_DIR_U)
#define GE_MAJ_AXIS_Y 0x000000100
#define GE_SRC_LINEAR 0x000000A00
#define GE_SRC_VAR_PITCH 0x000000200
#define GE_SRC_PATTERN 0x000000400
#define GE_SRC_MONO 0x000001000
#define GE_SRC_XPARENT 0x000002000
#define GE_PIX_DEPTH_16 0x000008000
#define GE_24BPP 0x000010000
#define GE_VAR_STRIDE_BPP 0x000014000
#define GE_DST_CONTIGUOUS 0x000080000
#define GE_DST_LINEAR 0x0000C0000
#define GE_DST_VAR_PITCH 0x000040000
#define GE_VAR_PITCH 0x000060200
#define GE_PAT_COLOR 0x000400000
#define GE_MODEL_640 0x001000000
#define GE_MODEL_800 0x002000000
#define GE_MODEL_1024 0x004000000
#define GE_MODEL_1152 0x005000000
#define GE_MODEL_1280 0x006000000
#define GE_MODEL_1600 0x007000000
#define GE_DEST_UPDATE_TR 0x008000000
#define GE_DEST_UPDATE_BL 0x010000000
#define GE_DEST_UPDATE_LP 0x018000000
#define GE_START_ON_XEXT 0x020000000
#define GE_START_ON_SRCX 0x040000000
#define GE_START_ON_DESTX 0x060000000
#define GE_BLT_START 0x080000000
#define ALIGN_4_UP(x) ((x + 3) & ~3)
#define ALIGN_4_DN(x) (x & ~3)
#define DW_ALIGN_PIXELS 3
#define DDST 0xaa
#define SSRC 0xCC
#define PPAT 0xCC
#define ROP_D (DDST)
#define ROP_DDx (DDST ^ DDST)b
#define ROP_DPon (~(DDST | PPAT))
#define ROP_DPna (DDST & (~ PPAT))
#define ROP_Pn (~PPAT)
#define ROP_DSon (~(DDST | SSRC))
#define ROP_DSna (DDST & (~SSRC))
#define ROP_Sn (~SSRC)
#define ROP_DnSa (~DDST) & SSRC
#define ROP_DnPa (~DDST) & PPAT
#define ROP_Dfn (~DDST)
#define ROP_DPx (DDST ^ PPAT)
#define ROP_DPan (~(DDST & PPAT))
#define ROP_DSx (DDST ^ SSRC)
#define ROP_DSan (~(DDST & SSRC))
#define ROP_DSa (DDST & SSRC)
#define ROP_DSxn (~(DDST ^ SSRC))
#define ROP_DSno (DDST | (~ SSRC)b)
#define ROP_S (SSRC)
#define ROP_DnSo ((~DDST) | SSRC)
#define ROP_DSo (DDST | SSRC)
#define ROP_DDxn (~(DDST ^ DDST))
#define ROP_0 (DDST ^ DDST)
#define ROP_1 (~(DDST ^ DDST))
#define ROP_P (PPAT)
/* waits until cNeed FIFO entries are available */
#define FIFOWait(cNeed) while((lpCOP->cFIFOEntries & 0xF) < cNeed);
/* Additionnal Defines for 2nd version of motion video hardware */
enum{
HWOVERLAY_V1,
HWOVERLAY_V2
};
#define TILE_PRECISION 4096
#define OVLY2_SUCCESS 1
#define OVLY2_FAILURE 0
enum{
HW2D_V1,
HW2D_V2
};
/* Flags for passing info between 16 and 32 bit sides of Direct Draw. */
#define SI_LINEAR_MEMORY 0x00000001
#define SI_DRIVER_DESTROYED 0x00000002
#define SI_ENABLE_HOR_INTERP 0x00000004
#define SI_ENABLE_VER_INTERP 0x00000008
/* 3D Polygon Engine Control bits */
#define _3DCTRL_QUICKSTART_POLYLIST 0x00000004
#define _3DCTRL_QUICKSTART_POLYSTRIP 0x00000006
#define _3DCTRL_TLUT_LOAD 0x00000008
#define _3DCTRL_TEXTURE_ENABLE 0x00000010
#define _3DCTRL_TEXTURE_JITTER_ENABLE 0x00000020
#define _3DCTRL_TEXTURE_DITHER_ENABLE 0x00000040
#define _3DCTRL_FEEDFORWARD_DITHER_ENABLE 0x00000080
#define _3DCTRL_TEXT_TRANSPARENCY_ENABLE 0x00000100
#define _3DCTRL_GOURAUD_ENABLE 0x00000200
#define _3DCTRL_LIGHTING_ENABLE 0x00000400
#define _3DCTRL_FOG_ENABLE 0x00000800
#define _3DCTRL_DEST_8_INDEXED 0x00002000
#define _3DCTRL_DEST_8_DIRECT 0x00003000
#define _3DCTRL_DEST_15_DIRECT 0x00004000
#define _3DCTRL_DEST_16_DIRECT 0x00005000
#define _3DCTRL_DEST_32_DIRECT 0x00007000
#define _3DCTRL_STIPPLED_ALPHA_ENABLE 0x00008000
#define _3DCTRL_ZBUFFER_READ_ENABLE 0x00010000
#define _3DCTRL_ZBUFFER_WRITE_ENABLE 0x00020000
#define _3DCTRL_ZBUFFER_TILED 0x00040000
#define _3DCTRL_MIPMAP_ENABLE 0x00080000
#define _3DCTRL_CLIPPING_ENABLE 0x00100000
#define _3DCTRL_DISABLE_ANTITEARING 0x00200000
#define _3DCTRL_GRADIENT_REINT_ENABLE 0x00800000
#define _3DCTRL_BBCTRL_ANY 0x02000000
#define _3DCTRL_BBCTRL_BOTH 0x03000000
#define _3DCTRL_BBCHK_ALL_INV 0x04000000
#define _3DCTRL_BBCHK_ALL_VIS 0x08000000
#define _3DCTRL_BBCHK_SOME_VIS 0x0C000000
#define _3DCTRL_HRES320 0x00000000
#define _3DCTRL_HRES512 0x30000000
#define _3DCTRL_HRES640 0x10000000
#define _3DCTRL_HRES800 0x20000000
#define _3DCTRL_HRES1024 0x40000000
#define _3DCTRL_HRES1152 0x50000000
#define _3DCTRL_HRES1280 0x60000000
#define _3DCTRL_HRES1600 0x70000000
#define _3DCTRL_POLYGON_START 0x80000000
#define _3DCTRL_HRES_MASK 3DCTRL_HRES1600
/* 3D Polygon Engine Control Register 2 bits */
#define _3DCTRL2_TEXTURE_MIRROR 0x00000040
#define _3DCTRL2_TEXTURE_CLAMP 0x00000080
#define _3DCTRL2_SRC_TEXTURE_ALPHA 0x00000200
/* alpha default is 0FFh == opaque */
#define _3DCTRL2_REVERSE_ALPHA 0x00000400
#define _3DCTRL2_DISABLE_UV_CLAMP 0x08000000
#define _3DCTRL2_ZCMP_NEVER 0x00000000
#define _3DCTRL2_ZCMP_LESS 0x00002000
#define _3DCTRL2_ZCMP_EQUAL 0x00004000
#define _3DCTRL2_ZCMP_LESSEQUAL 0x00006000
#define _3DCTRL2_ZCMP_GREATER 0x00008000
#define _3DCTRL2_ZCMP_NOTEQUAL 0x0000A000
#define _3DCTRL2_ZCMP_GREATEREQUAL 0x0000C000
#define _3DCTRL2_ZCMP_ALWAYS 0x0000E000
#define _MinIdxGRADIENT 0x000004
#define _MajIdxZ 0x000020
#define _MajIdxW 0x000030
#define _MajIdxL 0x000040
#define _MajIdxUW 0x000060
#define _MajIdxVW 0x000070
#define _WEnableZ 0x020000
#define _WEnableW 0x040000
#define _WEnableL 0x080000
#define _WEnableUW 0x200000
#define _WEnableVW 0x400000
/* 3D Texture Format register fields */
#define TEXTURE_4B 0x1 /* indexed */
#define TEXTURE_8B 0x2
#define TEXTURE_15B 0x4 /* direct */
#define TEXTURE_16B 0x5
#define TEXTURE_32B 0x7 /* XRGB */
#define TEXTURE_ARGB_4444 0xB /* ARGB 4444 */
#define TEXTURE_ARGB_1555 0xC /* ARGB 1555 */
#define TEXTURE_WIDTH_8 0<<5
#define TEXTURE_WIDTH_16 1<<5
#define TEXTURE_WIDTH_32 2<<5
#define TEXTURE_WIDTH_64 3<<5
#define TEXTURE_WIDTH_128 4<<5
#define TEXTURE_WIDTH_256 5<<5
#define TEXTURE_HEIGHT_8 0<<8
#define TEXTURE_HEIGHT_16 1<<8
#define TEXTURE_HEIGHT_32 2<<8
#define TEXTURE_HEIGHT_64 3<<8
#define TEXTURE_HEIGHT_128 4<<8
#define TEXTURE_HEIGHT_256 5<<8
/* Texture Look-up Table (TLUT) defines */
#define TLUT_LINEAR_OFFSET 0xFFF400 /* location with 16MB PCI memory space */
#define N_TLUT_ENTRIES 256
#define TLUT_ENTRY FxU32
#define MAKE_TLUT_DATA(Red,Green,Blue) ((FxU32)(Red) << 16) | ((FxU32)(Green) << 8) | (FxU32)(Blue)
/* ExtendedMemoryEnable register Bits */
#define ENABLE_EXTENDED_MEMORY_DOS 0x1
#define ENABLE_EXTENDED_MEMORY_LINEAR 0x2
#define ENABLE_EXTENDED_MEMORY_COPROC 0x4
#define ENABLE_EXTENDED_MEMORY_SECOND_AP 0x8
/* PUMA defines */
#define PUMA_CONTROL_OFF 0x0
#define PUMA_CONTROL_SFB 0x1
#define PUMA_CONTROL_ON 0x3
/* GPIO defines */
#define GPIO_PUMA_SRESET_N 0x10
#define GPIO_PUMA_SWAP 0x40
/* VGA Override defines */
#define VGA_OVERRIDE_DISABLE_DRAM_REFRESH 0x800
/* Mem Config Register defines */
#define MEMCONFIG_ENABLE_SINGLE_CYCLE 0x400
#pragma pack()

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glide2x/sst1/init/init96/prefresh.h Normal file
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/////////////////////////////////////////////////////////////////////////////
//
// PREFRESH.H
//
// This module contains refresh values for ProMotion.
//
// Copyright 1994-1996 Alliance Semiconductor Corporation
//
/////////////////////////////////////////////////////////////////////////////
#ifndef WORD
typedef unsigned short WORD;
#endif
#ifndef BYTE
typedef unsigned char BYTE;
#endif
#ifndef _REFRESH_DEFS
#define _REFRESH_DEFS
#pragma pack(1)
// FIFO Overflow registers.
typedef struct{
BYTE HRM;
BYTE HRNM;
BYTE LR;
BYTE VClk; // Vclk for 3210, based on pixel depth
}OVERFLOW, *POVERFLOW;
// Values for a particular resolution,refresh, bitdepth.
typedef struct{
int VRefresh;
WORD HTotal;
WORD HDispEnd;
WORD HBlankStart;
WORD HSyncStart;
WORD HSyncEnd;
WORD HBlankEnd;
WORD VTotal;
WORD VDispEnd;
WORD VBlankStart;
WORD VSyncStart;
WORD VSyncEnd;
WORD VBlankEnd;
WORD VOverflow;
BYTE MiscOutput; // h,v polarity for refresh rate
BYTE VClk; // vclk for chips >= 6422
OVERFLOW OverFlow[5]; // Overflow FIFO values for 8,16,32
}REF_TABLE, *PREF_TABLE;
// Video Clocks for CH9294 Version G
enum{
VC_25,VC_28,VC_40,VC_72,VC_50,VC_XX,VC_36,VC_45,VC_130,
VC_120,VC_80,VC_31,VC_110,VC_65,VC_75,VC_94,VC_100,VC_135,
VC_144,VC_160,VC_188,VC_47,VC_56,VC_49,VC_78,VC_108,VC_157,
VC_175,VC_202,VC_41,VC_53,VC_77
};
#pragma pack()
#endif // _REFRESH_DEFS
#ifdef DEFINE_REFRESH_DATA
#define NA 255
#define INVALID_MODE 255
unsigned short aIndexToVClk[] = {
25, // VC_25,
28, // VC_28,
40, // VC_40,
72, // VC_72,
50, // VC_50,
00, // VC_XX,
36, // VC_36,
45, // VC_45,
130, // VC_130,
120, // VC_120,
80, // VC_80,
31, // VC_31,
110, // VC_110,
65, // VC_65,
75, // VC_75,
94, // VC_94,
100, // VC_100,
135, // VC_135,
144, // VC_144,
160, // VC_160,
188, // VC_188,
47, // VC_47,
56, // VC_56,
49, // VC_49,
78, // VC_78,
108, // VC_108,
157, // VC_157,
175, // VC_175,
202, // VC_202,
41, // VC_41,
53, // VC_53,
77 // VC_77
};
// Tables of CRTC adjustments to a mode for a specified refresh.
REF_TABLE aRefUnsupported[]={
{0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000, 0x000, 0x000, 0x000, 0x0, 0x00, 0x00, 0x00, VC_50,
{{11,7,21,VC_50},{28,19,30,VC_110},{INVALID_MODE}}}
};
REF_TABLE aRef640x480[]={
{60, 0x5F, 0x4F, 0x50, 0x52, 0x1E, 0x22, 0x20B, 0x1DF, 0x1E7, 0x1EA, 0xC, 0x04, 0x3E, 0xC0,VC_25,
{{1,0,16,VC_25},{3,2,17,VC_50},{10,6,21,VC_75},{0,2,0,VC_75},{1,0,16,VC_25}}},
{72, 0x62, 0x4F, 0x50, 0x52, 0x17, 0x26, 0x206, 0x1DF, 0x1E7, 0x1E8, 0xB, 0xFF, 0x3E, 0xC0,VC_31,
{{1,0,16,VC_31},{6,3,19,VC_65},{15,10,23,VC_94},{0,2,0,VC_94},{1,0,16,VC_31}}},
{75, 0x63, 0x4F, 0x50, 0x51, 0x19, 0x27, 0x1F2, 0x1DF, 0x1E0, 0x1E0, 0x3, 0xF2, 0x1F, 0xC0,VC_31,
{{1,0,16,VC_31},{6,3,19,VC_65},{15,10,23,VC_94},{0,2,0,VC_94},{1,0,16,VC_31}}},
/* Removed for all chips prior to 6424, 85Hz is available for 6422 if VesaTimings Switch is set for VESA Table
{85, 0x62, 0x4F, 0x50, 0x53, 0x19, 0x26, 0x1FB, 0x1DF, 0x1E0, 0x1E0, 0x3, 0xFB, 0x1F, 0xC0,VC_36,
{{1,0,16,VC_36},{6,3,19,VC_72},{15,10,23,VC_110},{0,2,0,VC_110}}},
{100, 0x5F, 0x4F, 0x50, 0x55, 0x1D, 0x22, 0x206, 0x1DF, 0x1E0, 0x1E5, 0xA, 0xF9, 0x3E, 0xC0,VC_41,
{{4,3,17,VC_40},{9,6,20,VC_80},{18,13,24,VC_120},{3,5,1,VC_120}}},
{120, 0x63, 0x4F, 0x50, 0x54, 0x02, 0x24, 0x217, 0x1DF, 0x1E0, 0x1E4, 0x1, 0x0A, 0x3E, 0xC0,VC_53,
{{7,6,19,VC_94},{12,9,22,VC_108},{21,16,26,VC_157},{6,8,3,VC_157}}},
*/
{0}
};
REF_TABLE aRef640x480VESA[]={
{60, 0x5F, 0x4F, 0x50, 0x52, 0x1E, 0x22, 0x20B, 0x1DF, 0x1E7, 0x1E9, 0xB, 0x04, 0x3E, 0xC0,VC_25,
{{1,0,16,VC_25},{3,2,17,VC_50},{10,6,21, VC_75},{0,2,0,VC_75},{1,0,16,VC_25}}},
{72, 0x63, 0x4F, 0x50, 0x53, 0x18, 0x27, 0x206, 0x1DF, 0x1E7, 0x1E8, 0xB, 0xFF, 0x3E, 0xC0,VC_31,
{{1,0,16,VC_31},{6,3,19,VC_65},{15,10,23,VC_94},{0,2,0,VC_94},{1,0,16,VC_31}}},
{75, 0x64, 0x4F, 0x50, 0x52, 0x1A, 0x27, 0x1F2, 0x1DF, 0x1E0, 0x1E0, 0x3, 0xF2, 0x1F, 0xC0,VC_31,
{{1,0,16,VC_31},{6,3,19,VC_65},{15,10,23,VC_94},{0,2,0,VC_94},{1,0,16,VC_31}}},
{85, 0x63, 0x4F, 0x50, 0x54, 0x1A, 0x27, 0x1FB, 0x1DF, 0x1E0, 0x1E0, 0x3, 0xFB, 0x1F, 0xC0,VC_36,
{{2,1,17,VC_36},{6,4,19,VC_72},{17,11,24,VC_110},{0,2,0,VC_110},{2,1,17,VC_36}}},
{100, 0x5F, 0x4F, 0x50, 0x55, 0x1D, 0x22, 0x206, 0x1DF, 0x1E0, 0x1E5, 0xA, 0xF9, 0x3E, 0xC0,VC_41,
{{4,3,17,VC_40},{9,6,20,VC_80},{18,13,24,VC_120},{3,5,1,VC_120},{4,3,17,VC_40}}},
{120, 0x63, 0x4F, 0x50, 0x54, 0x02, 0x24, 0x217, 0x1DF, 0x1E0, 0x1E4, 0x1, 0x0A, 0x3E, 0xC0,VC_53,
{{7,6,19,VC_94},{12,9,21,VC_108},{21,16,25,VC_157},{6,8,3,VC_157},{7,6,19,VC_94}}},
{0}
};
REF_TABLE aRef800x600[]={
{56, 0x7B, 0x63, 0x64, 0x66, 0x0F, 0x3E, 0x26F, 0x257, 0x258, 0x258, 0xA, 0x6F, 0xF0, 0x0,VC_36,
{{2,1,17,VC_36},{6,4,19,VC_72},{17,11,24,VC_72},{0,9,0,VC_72},{2,1,17,VC_36}}},
{60, 0x80, 0x63, 0x64, 0x68, 0x18, 0x02, 0x272, 0x257, 0x258, 0x258, 0xC, 0x72, 0xF0, 0x0,VC_40,
{{2,1,17,VC_40},{7,4,19,VC_80},{19,12,25,VC_80},{0,9,0,VC_80},{2,1,17,VC_40}}},
{72, 0x7D, 0x63, 0x64, 0x6A, 0x19, 0x00, 0x29C, 0x257, 0x258, 0x27C, 0x2, 0x9C, 0xF0, 0x0,VC_50,
{{3,2,17,VC_50},{17,17,20,VC_94},{25,19,27,VC_94},{0,9,0,VC_94},{3,2,17,VC_50}}},
{75, 0x7F, 0x63, 0x64, 0x65, 0x0F, 0x02, 0x26F, 0x257, 0x258, 0x258, 0xB, 0x6F, 0xF0, 0x0,VC_50,
{{3,2,17,VC_50},{17,17,20,VC_94},{25,19,27,VC_94},{0,9,0,VC_94},{3,2,17,VC_50}}},
/* Removed for all chips prior to 6424, 85Hz is available for 6422 if VesaTimings Switch is set for VESA Table
{85, 0x7F, 0x63, 0x64, 0x65, 0x0F, 0x02, 0x26F, 0x257, 0x258, 0x258, 0xB, 0x6F, 0xF0, 0x0,VC_56,
{{3,2,17,VC_56},{17,17,20,VC_94},{INVALID_MODE},{INVALID_MODE}}},
// {{3,2,17,VC_56},{17,17,20,VC_94},{25,19,28,VC_94},{0,8,0,VC_94}}},
{100, 0x79, 0x63, 0x64, 0x66, 0x12, 0x3C, 0x285, 0x257, 0x258, 0x25F, 0xE, 0x7A, 0xF0, 0x0,VC_65,
{{6,5,18,VC_56},{20,20,21,VC_130},{INVALID_MODE},{INVALID_MODE}}},
{120, 0x7A, 0x63, 0x64, 0x68, 0x11, 0x3D, 0x277, 0x257, 0x258, 0x25C, 0xE, 0x6E, 0xF0, 0x0,VC_77,
{{9,8,20,VC_56},{23,23,23,VC_157},{INVALID_MODE},{INVALID_MODE}}},
*/
{0}
};
REF_TABLE aRef800x600VESA[]={
{56, 0x7B, 0x63, 0x64, 0x67, 0x10, 0x3E, 0x26F, 0x257, 0x258, 0x258, 0xA, 0x6F, 0xF0, 0x0,VC_36,
{{2,1,17,VC_36},{6,4,19,VC_72},{17,11,24,VC_72},{0,9,0,VC_72},{2,1,17,VC_36}}},
{60, 0x7F, 0x63, 0x63, 0x69, 0x19, 0x03, 0x272, 0x257, 0x258, 0x258, 0xC, 0x72, 0xF0, 0x0,VC_40,
{{2,1,17,VC_40},{7,4,19,VC_80},{19,12,25,VC_80},{0,9,0,VC_80},{2,1,17,VC_40}}},
{72, 0x7D, 0x63, 0x64, 0x6B, 0x1A, 0x01, 0x298, 0x257, 0x258, 0x27C, 0x2, 0x98, 0xF0, 0x0,VC_50,
{{3,2,17,VC_50},{17,17,20,VC_94},{25,19,27,VC_94},{0,9,0,VC_94},{3,2,17,VC_50}}},
{75, 0x7F, 0x63, 0x63, 0x66, 0x10, 0x02, 0x26F, 0x257, 0x258, 0x258, 0xB, 0x6F, 0xF0, 0x0,VC_49,
{{3,2,17,VC_49},{17,17,20,VC_94},{25,19,27,VC_94},{0,9,0,VC_94},{3,2,17,VC_49}}},
{85, 0x7E, 0x63, 0x63, 0x68, 0x10, 0x02, 0x275, 0x257, 0x258, 0x258, 0xB, 0x76, 0xF0, 0x0,VC_56,
{{4,2,18,VC_56},{11,7,21,VC_110},{9,9,20,VC_94},{INVALID_MODE},{4,2,18,VC_56}}},
//{{4,2,18,VC_56},{11,7,21,VC_110},{25,19,28,VC_94},{0,8,0,VC_94}}},
{100, 0x79, 0x63, 0x64, 0x66, 0x12, 0x3C, 0x285, 0x257, 0x258, 0x25F, 0xE, 0x7A, 0xF0, 0x0,VC_65,
{{6,5,18,VC_56},{20,20,21,VC_130},{12,11,21,VC_120},{INVALID_MODE},{6,5,18,VC_56}}},
{120, 0x7A, 0x63, 0x64, 0x68, 0x11, 0x3D, 0x277, 0x257, 0x258, 0x25C, 0xE, 0x6E, 0xF0, 0x0,VC_77,
{{9,8,20,VC_56},{23,23,23,VC_157},{INVALID_MODE},{INVALID_MODE},{9,8,20,VC_56}}},
{0}
};
REF_TABLE aRef1024x768[]={
{43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000, 0x000, 0x000, 0x000, 0x0, 0x00, 0x00, 0x00,VC_45,
{{2,0,17,VC_45},{9,5,21,VC_45},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE}}},
{60, 0xA2, 0x7F, 0x80, 0x82, 0x13, 0x26, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0xC0,VC_65,
{{5,3,18,VC_65},{15,9,23,VC_65},{INVALID_MODE},{INVALID_MODE},{5,3,18,VC_65}}},
{70, 0xA1, 0x7F, 0x80, 0x82, 0x13, 0x24, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0xC0,VC_75,
{{6,4,19,VC_75},{17,11,24,VC_75},{INVALID_MODE},{INVALID_MODE},{6,4,19,VC_75}}},
{72, 0xA4, 0x7F, 0x80, 0x81, 0x12, 0x24, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0x0, VC_78,
{{7,4,19,VC_80},{18,12,25,VC_80},{INVALID_MODE},{INVALID_MODE},{7,4,19,VC_80}}},
{75, 0xA3, 0x7F, 0x80, 0x83, 0x0F, 0x22, 0x31E, 0x2FF, 0x300, 0x300, 0x3, 0x1E, 0xFD, 0x0, VC_78,
{{7,4,19,VC_80},{19,12,25,VC_80},{INVALID_MODE},{INVALID_MODE},{7,4,19,VC_80}}},
/* Removed for all chips prior to 6424, 85Hz is available for 6422 if VesaTimings Switch is set for VESA Table
{85, 0xA6, 0x7F, 0x80, 0x85, 0x0F, 0x22, 0x31E, 0x2FF, 0x300, 0x300, 0x3, 0x1E, 0xFD, 0x0, VC_94,
{{7,4,19,VC_94},{19,12,25,VC_94},{INVALID_MODE}}},
{100, 0xA3, 0x7F, 0x80, 0x81, 0x0C, 0x11, 0x330, 0x2FF, 0x300, 0x307, 0x9, 0x2D, 0xFD, 0x0, VC_108,
{{10,7,21,VC_108},{INVALID_MODE},{INVALID_MODE}}},
*/
{0}
};
REF_TABLE aRef1024x768VESA[]={
{43, 0x99, 0x7f, 0x80, 0x81, 0x17, 0x9c, 0x32f, 0x2ff, 0x300, 0x300, 0x8, 0x2e, 0xfd, 0x00,VC_45,
{{2,0,17,VC_45},{9,5,21,VC_45},{10,10,20,VC_45},{INVALID_MODE},{INVALID_MODE}}},
{60, 0xA3, 0x7F, 0x7F, 0x83, 0x14, 0x27, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0xC0,VC_65,
{{5,3,18,VC_65},{15,9,23,VC_65},{11,11,21},{11,11,21},{5,3,18,VC_65}}},
{70, 0xA1, 0x7F, 0x7F, 0x83, 0x14, 0x24, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0xC0,VC_75,
{{6,4,19,VC_75},{17,11,24,VC_75},{13,13,23},{13,13,23},{6,4,19,VC_75}}},
{72, 0xA4, 0x7F, 0x80, 0x81, 0x12, 0x24, 0x324, 0x2FF, 0x300, 0x302, 0x8, 0x24, 0xFD, 0x0, VC_78,
{{7,4,19,VC_80},{18,12,25,VC_80},{14,14,24},{14,14,24},{7,4,19,VC_80}}},
{75, 0x9F, 0x7F, 0x7F, 0x82, 0x0E, 0x23, 0x31E, 0x2FF, 0x300, 0x300, 0x3, 0x1E, 0xFD, 0x0, VC_78,
{{7,4,19,VC_80},{19,12,25,VC_80},{16,16,25},{16,16,25},{7,4,19,VC_80}}},
{85, 0xA7, 0x7F, 0x7F, 0x86, 0x12, 0x2A, 0x326, 0x2FF, 0x300, 0x300, 0x3, 0x27, 0xFD, 0x0, VC_94,
{{7,4,19,VC_94},{19,12,25,VC_94},{18,18,27},{18,18,27},{7,4,19,VC_94}}},
{100, 0xA1, 0x7F, 0x80, 0x81, 0x0C, 0x11, 0x330, 0x2FF, 0x300, 0x307, 0x9, 0x2D, 0xFD, 0x0, VC_108,
{{12,9,22,VC_108},{7,7,19,VC_108},{INVALID_MODE},{INVALID_MODE},{12,9,22,VC_108}}},
{0}
};
REF_TABLE aRef1152x864[]={
{60, 0xB4, 0x8F, 0x90, 0x94, 0x04, 0x37, 0x382, 0x35F, 0x360, 0x360, 0x3, 0x82, 0xFF, 0x0,VC_80,
{{7,4,19,VC_80},{19,12,25,VC_80},{INVALID_MODE},{INVALID_MODE},{7,4,19,VC_80}}},
{70, 0xB4, 0x8F, 0x90, 0x94, 0x00, 0x38, 0x38E, 0x35F, 0x360, 0x360, 0x3, 0x8F, 0xFF, 0x0,VC_94,
{{9,6,20,VC_94},{22,15,27,VC_94},{INVALID_MODE},{INVALID_MODE},{9,6,20,VC_94}}},
{72, 0xB1, 0x8F, 0x90, 0x94, 0x04, 0x34, 0x382, 0x35F, 0x360, 0x360, 0x3, 0x82, 0xFF, 0x0,VC_94,
{{9,6,20,VC_94},{22,15,27,VC_94},{INVALID_MODE},{INVALID_MODE},{9,6,20,VC_94}}},
{75, 0xB4, 0x8F, 0x90, 0x97, 0x07, 0x37, 0x382, 0x35F, 0x360, 0x360, 0x3, 0x82, 0xFF, 0x0,VC_100,
{{11,7,21,VC_110},{28,19,30,VC_110},{INVALID_MODE},{INVALID_MODE},{11,7,21,VC_110}}},
/* Removed for all chips prior to 6424, 85Hz is available for 6422 if VesaTimings Switch is set for VESA Table
{85, 0xBF, 0x8F, 0x90, 0x98, 0x08, 0x03, 0x388, 0x35F, 0x360, 0x361, 0x4, 0x89, 0xFF, 0x0,VC_120,
{{14,10,22,VC_120},{31,22,31,VC_120},{INVALID_MODE}}},
*/
{0}
};
REF_TABLE aRef1152x864VESA[]={
{60, 0xB4, 0x8F, 0x90, 0x94, 0x04, 0x37, 0x382, 0x35F, 0x360, 0x360, 0x3, 0x82, 0xFF, 0x0,VC_80,
{{7,4,19,VC_80},{19,12,25,VC_80},{17,17,25},{17,17,25},{7,4,19,VC_80}}},
{70, 0xB4, 0x8F, 0x90, 0x94, 0x00, 0x38, 0x38E, 0x35F, 0x360, 0x360, 0x3, 0x8F, 0xFF, 0x0,VC_94,
{{9,6,20,VC_94},{22,15,27,VC_94},{19,19,27},{19,19,27},{9,6,20,VC_94}}},
{75, 0xC3, 0x8F, 0x90, 0x98, 0x08, 0x36, 0x382, 0x35F, 0x360, 0x360, 0x3, 0x82, 0xFF, 0x0,VC_108,
{{11,7,21,VC_108},{9,8,19,VC_120},{INVALID_MODE},{INVALID_MODE},{11,7,21,VC_108}}},
{85, 0xBF, 0x8F, 0x90, 0x98, 0x08, 0x03, 0x388, 0x35F, 0x360, 0x361, 0x4, 0x89, 0xFF, 0x0,VC_120,
{{14,10,22,VC_120},{8,8,19,VC_120},{INVALID_MODE},{INVALID_MODE},{14,10,22,VC_120}}},
{0}
};
REF_TABLE aRef1280x1024[]={
{43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000, 0x000, 0x000, 0x000, 0x0, 0x00, 0x00, 0x0,VC_75,
{{6,3,19,VC_75},{15,9,24,VC_75},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE}}},
/*
{60, 0xC2, 0x9F, 0xA0, 0xA1, 0x15, 0x02, 0x029, 0x3FF, 0x000, 0x001, 0x5, 0x29, 0x52, 0x0,VC_100,
{{12,8,22,VC_50},{INVALID_MODE},{INVALID_MODE}}},
{60, 0xD3, 0x9F, 0xA0, 0xAB, 0x1F, 0x16, 0x029, 0x3FF, 0x000, 0x001, 0x5, 0x29, 0x52, 0x0,VC_108,
{{INVALID_MODE},{26,18,27,VC_108},{INVALID_MODE}}},
*/
//VESA Settings for 60 Hz
{60, 0xCE, 0x9F, 0x9F, 0xA6, 0x14, 0x12, 0x028, 0x3FF, 0x3FF, 0x000, 0x3, 0x29, 0x52, 0x0, VC_108,
{{12,8,22,VC_50},{26,18,27,VC_110},{INVALID_MODE},{INVALID_MODE},{12,8,22,VC_50}}},
{72, 0xCE, 0x9F, 0xA0, 0xA2, 0x16, 0x11, 0x029, 0x3FF, 0x000, 0x001, 0x5, 0x29, 0x52, 0x0,VC_130,
{{15,9,23,VC_65},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE},{15,9,23,VC_65}}},
//VESA Settings for 75 Hz
{75, 0xCE, 0x9F, 0x9F, 0xA2, 0x14, 0x12, 0x028, 0x3FF, 0x3FF, 0x000, 0x3, 0x28, 0x52, 0x0, VC_135,
{{15,9,23,VC_72},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE},{15,9,23,VC_72}}},
//{75, 0xDC, 0x9F, 0xA0, 0xA2, 0x16, 0x1F, 0x029, 0x3FF, 0x000, 0x001, 0x5, 0x29, 0x52, 0x0,VC_135,
//{{15,9,23,VC_72},{INVALID_MODE},{INVALID_MODE}}},
/* Removed for all chips prior to 6424, 85Hz is available for 6422 if VesaTimings Switch is set for VESA Table
{85, 0xD2, 0x9F, 0x9F, 0xA5, 0x19,0x15, 0x02C, 0x3FF, 0x3FF, 0x000, 0x3, 0x2D, 0x5A, 0x0, VC_157,
{{18,12,24,VC_157},{INVALID_MODE},{INVALID_MODE}}},
*/
{0}
};
REF_TABLE aRef1280x1024VESA[]={
{43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000, 0x000, 0x000, 0x000, 0x0, 0x00, 0x00, 0x0, VC_75,
{{6,3,19,VC_75},{5,5,18,VC_75},{INVALID_MODE},{INVALID_MODE},{6,3,19,VC_75}}},
{60, 0xCE, 0x9F, 0x9F, 0xA6, 0x14, 0x12, 0x028, 0x3FF, 0x3FF, 0x000, 0x3, 0x29, 0x52, 0x0, VC_108,
{{12,8,22,VC_50},{7,7,19,VC_110},{INVALID_MODE},{19,19,27},{12,8,22,VC_50}}},
{72, 0xCE, 0x9F, 0xA0, 0xA2, 0x16, 0x11, 0x029, 0x3FF, 0x000, 0x001, 0x5, 0x29, 0x52, 0x0, VC_130,
{{15,9,23,VC_65},{10,10,20,VC_65},{INVALID_MODE},{INVALID_MODE},{15,9,23,VC_65}}},
{75, 0xCE, 0x9F, 0x9F, 0xA2, 0x14, 0x12, 0x028, 0x3FF, 0x3FF, 0x000, 0x3, 0x28, 0x52, 0x0, VC_135,
{{15,9,23,VC_72},{10,10,20,VC_65},{INVALID_MODE},{INVALID_MODE},{15,9,23,VC_72}}},
{85, 0xD2, 0x9F, 0x9F, 0xA5, 0x19,0x15, 0x02C, 0x3FF, 0x3FF, 0x000, 0x3, 0x2D, 0x5A, 0x0, VC_157,
{{18,12,24,VC_157},{13,12,21,VC_157},{INVALID_MODE},{INVALID_MODE},{18,12,24,VC_157}}},
{0}
};
REF_TABLE aRef1600x1200[]={
{43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000, 0x000, 0x000, 0x000, 0x0, 0x00, 0x00, 0x00,VC_135,
{{4,4,17,VC_45},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE}}},
{60, 0x09, 0xC7, 0xC8, 0xCB, 0x1F, 0x0C, 0x0E0, 0x0AF, 0x0B0, 0x0B0, 0x3, 0x0E0, 0x10, 0x0, VC_160,
{{18,12,25,VC_80},{14,14,22},{INVALID_MODE},{INVALID_MODE},{18,12,25,VC_80}}},
{65, 0x09, 0xC7, 0xC8, 0xCB, 0x1F, 0x0C, 0x0E0, 0x0AF, 0x0B0, 0x0B0, 0x3, 0x0E0, 0x10, 0x0, VC_175,
{{18,12,25,VC_80},{INVALID_MODE},{INVALID_MODE},{INVALID_MODE},{18,12,25,VC_80}}},
// {70, 0x09, 0xC7, 0xC8, 0xCB, 0x1F, 0x0C, 0x0E0, 0x0AF, 0x0B0, 0x0B0, 0x3, 0x0E0, 0x10, 0x0, VC_188,
// {{22,15,27,VC_94},{INVALID_MODE},{INVALID_MODE}}},
{0}
};
// Arrays of Non-VESA/VESA CRTC tables
REF_TABLE* apRefTables[]= {
aRef640x480,aRef800x600,aRef1024x768,aRef1152x864,aRef1280x1024,aRef1600x1200,aRefUnsupported};
REF_TABLE* apRefTablesVESA[]= {
aRef640x480VESA,aRef800x600VESA,aRef1024x768VESA,aRef1152x864VESA,aRef1280x1024VESA,aRef1600x1200,aRefUnsupported};
#ifdef REFRESH_CAPS // For Win95, refresh tables are moved here from physsetm.c.
// 8 bit
// Refresh rates available at specified Resolution
int aResAvailRefresh1[][CREFRESH] = {
{60,72,75,85,100,120,NA, NA}, //640x480
{56,60,72,75,85, 100,120,NA}, //800x600
{60,70,75,85,100,NA, NA, NA}, //1024x768
{60,70,75,85,NA, NA, NA, NA}, //1152x864
{60,72,75,85,NA, NA, NA, NA}, //1280x1024
{60,NA,NA,NA,NA, NA, NA, NA}, //1600x1200
{NA,NA,NA,NA,NA, NA, NA, NA} //Unsupported
};
// 16 bit
// Refresh rates available at specified Resolution
int aResAvailRefresh2[][CREFRESH]= {
{60,72,75,85,100,120,NA, NA}, //640x480
{56,60,72,75,85, 100,120,NA}, //800x600
{60,70,75,85,NA, NA, NA, NA}, //1024x768
{60,70,75,NA,NA, NA, NA, NA}, //1152x864
{60,72,75,85,NA, NA, NA, NA}, //1280x1024
{60,NA,NA,NA,NA, NA, NA, NA}, //1600x1200
{NA,NA,NA,NA,NA, NA, NA, NA} //Unsupported
};
// 24 bit
// Refresh rates available at specified Resolution
int aResAvailRefresh3[][CREFRESH] = {
{60,72,75,NA,NA, NA, NA, NA}, //640x480
{56,60,72,75,NA, NA, NA, NA}, //800x600
{60,70,75,85,NA, NA, NA, NA}, //1024x768
{60,70,NA,NA,NA, NA, NA, NA}, //1152x864
{60,NA,NA,NA,NA, NA, NA, NA}, //1280x1024
{NA,NA,NA,NA,NA, NA, NA, NA}, //1600x1200
{NA,NA,NA,NA,NA, NA, NA, NA} //Unsupported
};
// 32 bit
// Refresh rates available at specified Resolution
int aResAvailRefresh4[][CREFRESH] = {
{60,72,75,85,100,120,NA, NA}, //640x480
{56,60,72,75,85,100,120, NA}, //800x600
{60,70,75,85,NA, NA, NA, NA}, //1024x768
{60,70,NA,NA,NA, NA, NA, NA}, //1152x864
{NA,NA,NA,NA,NA, NA, NA, NA}, //1280x1024
{NA,NA,NA,NA,NA, NA, NA, NA}, //1600x1200
{NA,NA,NA,NA,NA, NA, NA, NA} //Unsupported
};
// 4 bit
// Refresh rates available at specified Resolution
int aResAvailRefresh5[][CREFRESH] = {
{60,72,75,85,100,120,NA, NA}, //640x480
{56,60,72,75,85, 100,120,NA}, //800x600
{60,70,75,85,100,NA, NA, NA}, //1024x768
{60,70,75,85,NA, NA, NA, NA}, //1152x864
{60,75,85,NA, NA,NA, NA, NA}, //1280x1024
{60,NA,NA,NA,NA, NA, NA, NA}, //1600x1200
{NA,NA,NA,NA,NA, NA, NA, NA} //Unsupported
};
PARES_AVAIL_REFRESH apaResAvailRefresh[]= {
aResAvailRefresh5, //4bpp
aResAvailRefresh1,
aResAvailRefresh2,
aResAvailRefresh3,
aResAvailRefresh4
};
#endif
#endif //_REFRESH_DATA