87 lines
2.4 KiB
C++
87 lines
2.4 KiB
C++
#include <systemc>
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#include <iostream>
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#include "EDORam.hpp"
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using namespace sc_core;
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using namespace sc_dt;
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SC_MODULE(Testbench) {
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sc_signal<bool> sigRAS, sigUCAS, sigLCAS, sigWE, sigOE;
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sc_signal< sc_uint<9> > sigADDR;
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sc_signal_rv<16> sigDATA; // resolved signal for bi-directional bus
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EDORam* ram;
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SC_CTOR(Testbench) {
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ram = new EDORam("edoram");
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ram->RAS(sigRAS);
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ram->UCAS(sigUCAS);
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ram->LCAS(sigLCAS);
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ram->WE(sigWE);
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ram->OE(sigOE);
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ram->ADDRESS(sigADDR);
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ram->DATA(sigDATA);
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SC_THREAD(run);
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}
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void run() {
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// init: all strobes inactive (true)
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sigRAS = true; sigUCAS = true; sigLCAS = true;
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sigWE = false; // choose WE=false as read, WE=true as write
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sigOE = true; // OE true => output disabled; OE false => output enabled
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sigADDR = 0;
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sigDATA.write("ZZZZZZZZZZZZZZZZ"); // high-Z
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wait(10, SC_NS);
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// WRITE cycle: write 0x1234 at addr 1
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unsigned addr = 1;
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uint16_t write_val = 0x1234;
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sigADDR = addr;
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// testbench drives data during write
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sc_lv<16> drive_val = sc_lv<16>( (uint64_t)write_val );
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sigDATA.write(drive_val);
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sigWE = true; // indicate write
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// RAS falling
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sigRAS = false;
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wait(5, SC_NS);
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// CAS falling (both)
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sigUCAS = false; sigLCAS = false;
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wait(5, SC_NS);
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// CAS rising
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sigUCAS = true; sigLCAS = true;
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wait(5, SC_NS);
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// RAS rising -> end
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sigRAS = true;
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// release testbench drive
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sigDATA.write("ZZZZZZZZZZZZZZZZ");
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sigWE = false;
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wait(10, SC_NS);
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// READ cycle: read addr 1
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sigADDR = addr;
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sigOE = false; // enable outputs from RAM when reading
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// RAS falling
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sigRAS = false;
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wait(5, SC_NS);
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// CAS falling
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sigUCAS = false; sigLCAS = false;
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wait(5, SC_NS);
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// sample data bus (RAM should drive)
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sc_lv<16> read_lv = sigDATA.read();
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uint16_t read_val = (uint16_t)read_lv.to_uint64();
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std::cout << "READ val = 0x" << std::hex << read_val << " expected 0x" << write_val << std::dec << std::endl;
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// finish
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sc_stop();
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}
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};
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int sc_main(int argc, char* argv[])
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{
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Testbench tb("tb");
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sc_start();
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return 0;
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} |