remove unittest for now
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@@ -1,137 +0,0 @@
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#include <systemc>
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#include <vector>
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using namespace sc_core;
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using namespace sc_dt;
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SC_MODULE(EDORam) {
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// ports (signals are active-low for strobes; true==inactive, false==asserted)
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sc_in<bool> RAS; // row strobe (active low)
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sc_in<bool> UCAS; // upper CAS (active low)
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sc_in<bool> LCAS; // lower CAS (active low)
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sc_in<bool> WE; // write enable (we treat WE==true as write for simplicity)
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sc_in<bool> OE; // output enable (not strictly required)
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sc_in< sc_uint<9> > ADDRESS; // address
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sc_inout_rv<16> DATA; // bidirectional data bus (resolved)
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SC_CTOR(EDORam)
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: addressWidth_(9), dataWidth_(16), memory_(1u << 9, 0)
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{
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SC_METHOD(process);
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sensitive << RAS << UCAS << LCAS << WE << OE << ADDRESS << DATA;
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dont_initialize();
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prevRAS_ = true;
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prevUCAS_ = true;
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prevLCAS_ = true;
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}
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private:
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enum State { WAIT_RAS, WAIT_CAS, WAIT_DATA };
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State state_{WAIT_RAS};
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const unsigned addressWidth_;
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const unsigned dataWidth_;
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std::vector<uint16_t> memory_;
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// previous values for edge detection (active-low strobes)
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bool prevRAS_;
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bool prevUCAS_;
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bool prevLCAS_;
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void process()
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{
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bool ras = RAS.read();
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bool ucas = UCAS.read();
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bool lcas = LCAS.read();
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bool we = WE.read(); // true => write (chosen convention)
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bool oe = OE.read();
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unsigned addr = ADDRESS.read();
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bool cas_asserted = (ucas == false && lcas == false); // CAS active when both low
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bool cas_any_low = (ucas == false || lcas == false);
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switch (state_) {
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case WAIT_RAS:
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// waiting for RAS falling edge (active low)
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if (prevRAS_ == true && ras == false) {
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state_ = WAIT_CAS;
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}
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break;
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case WAIT_CAS:
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// row is open, wait for CAS assertion (both low)
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if (ras == true) { // RAS rose -> abort/return to idle
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releaseDataBus();
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state_ = WAIT_RAS;
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}
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else if (prevUCAS_ == true && ucas == false && prevLCAS_ == true && lcas == false) {
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// CAS both fell -> enter data phase
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state_ = WAIT_DATA;
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performTransfer(addr, cas_asserted, we, oe);
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}
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break;
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case WAIT_DATA:
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// CAS low: data valid in EDO; continue to drive/sample while CAS low
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if (cas_asserted) {
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performTransfer(addr, cas_asserted, we, oe);
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}
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// CAS rising edge (both high) returns to WAIT_CAS (row still active)
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if (prevUCAS_ == false && ucas == true && prevLCAS_ == false && lcas == true) {
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releaseDataBus();
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state_ = WAIT_CAS;
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}
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// RAS rising -> precharge, go idle
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if (ras == true) {
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releaseDataBus();
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state_ = WAIT_RAS;
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}
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break;
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}
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prevRAS_ = ras;
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prevUCAS_ = ucas;
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prevLCAS_ = lcas;
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}
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void performTransfer(unsigned addr, bool cas_active, bool we, bool oe)
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{
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if (!cas_active) return; // only act when CAS is asserted (both low)
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if (we) {
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// WRITE: sample the data bus (testbench must drive DATA during write)
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sc_lv<16> val = DATA.read();
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// if testbench drives "Z" the conversion yields X; guard against that:
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bool has_x = false;
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for (unsigned i = 0; i < 16; ++i) {
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if (val[i] == sc_dt::SC_LOGIC_X) has_x = true;
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}
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if (!has_x) {
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uint16_t v = static_cast<uint16_t>(val.to_uint());
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if (addr < memory_.size()) memory_[addr] = v;
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}
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} else {
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// READ: drive the data bus with stored value (if OE allows)
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if (!oe) {
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// OE active (we treat OE==false as output enabled)
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uint16_t v = (addr < memory_.size()) ? memory_[addr] : 0;
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sc_lv<16> lv = sc_lv<16>( (uint64_t)v );
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DATA.write(lv);
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} else {
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// OE inactive -> leave bus high-Z
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releaseDataBus();
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}
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}
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}
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void releaseDataBus()
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{
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// drive high-impedance on resolved signal
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sc_lv<16> z;
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for (unsigned i = 0; i < 16; ++i) z[i] = sc_dt::SC_LOGIC_Z;
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DATA.write(z);
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}
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};
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@@ -1,44 +0,0 @@
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# Sim Unit Test Makefile
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CC := g++
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CFLAGS := -Wall -Wextra -std=gnu++17 -I/usr/local/include -g3 -ggdb
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LDFLAGS := -L/usr/local/lib -lm -lsystemc -lstdc++
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# Directories
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SRC_DIR := .
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BUILD_DIR := build
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BIN_DIR := bin
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# Source and object files
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SOURCES := $(wildcard $(SRC_DIR)/*.cpp)
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OBJECTS := $(SOURCES:$(SRC_DIR)/%.cpp=$(BUILD_DIR)/%.o)
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TARGET := $(BIN_DIR)/sim_test
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# Default target
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all: $(TARGET)
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# Create directories
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$(BUILD_DIR) $(BIN_DIR):
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mkdir -p $@
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# Link executable
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$(TARGET): $(OBJECTS) | $(BIN_DIR)
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$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
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# Compile objects
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$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp | $(BUILD_DIR)
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$(CC) $(CFLAGS) -c -o $@ $<
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# Run tests
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run: $(TARGET)
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./$(TARGET)
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# Clean build artifacts
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clean:
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rm -rf $(BUILD_DIR) $(BIN_DIR)
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# Phony targets
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.PHONY: all run clean
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test_EDORam.exe: $(BUILD_DIR)/test_EDORam.o
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$(CC) $(CFLAGS) -o $(BIN_DIR)/test_EDORam $^ $(LDFLAGS)
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@@ -1,10 +0,0 @@
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#include <systemc>
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//#include "EDORam.hpp"
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int main() {
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// build modules, bind ports, etc.
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sc_core::sc_start(100, sc_core::SC_NS); // run for 100 ns
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sc_core::sc_stop();
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return 0;
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}
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@@ -1,87 +0,0 @@
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#include <systemc>
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#include <iostream>
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#include "EDORam.hpp"
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using namespace sc_core;
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using namespace sc_dt;
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SC_MODULE(Testbench) {
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sc_signal<bool> sigRAS, sigUCAS, sigLCAS, sigWE, sigOE;
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sc_signal< sc_uint<9> > sigADDR;
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sc_signal_rv<16> sigDATA; // resolved signal for bi-directional bus
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EDORam* ram;
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SC_CTOR(Testbench) {
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ram = new EDORam("edoram");
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ram->RAS(sigRAS);
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ram->UCAS(sigUCAS);
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ram->LCAS(sigLCAS);
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ram->WE(sigWE);
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ram->OE(sigOE);
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ram->ADDRESS(sigADDR);
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ram->DATA(sigDATA);
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SC_THREAD(run);
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}
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void run() {
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// init: all strobes inactive (true)
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sigRAS = true; sigUCAS = true; sigLCAS = true;
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sigWE = false; // choose WE=false as read, WE=true as write
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sigOE = true; // OE true => output disabled; OE false => output enabled
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sigADDR = 0;
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sigDATA.write("ZZZZZZZZZZZZZZZZ"); // high-Z
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wait(10, SC_NS);
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// WRITE cycle: write 0x1234 at addr 1
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unsigned addr = 1;
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uint16_t write_val = 0x1234;
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sigADDR = addr;
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// testbench drives data during write
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sc_lv<16> drive_val = sc_lv<16>( (uint64_t)write_val );
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sigDATA.write(drive_val);
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sigWE = true; // indicate write
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// RAS falling
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sigRAS = false;
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wait(5, SC_NS);
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// CAS falling (both)
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sigUCAS = false; sigLCAS = false;
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wait(5, SC_NS);
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// CAS rising
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sigUCAS = true; sigLCAS = true;
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wait(5, SC_NS);
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// RAS rising -> end
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sigRAS = true;
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// release testbench drive
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sigDATA.write("ZZZZZZZZZZZZZZZZ");
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sigWE = false;
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wait(10, SC_NS);
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// READ cycle: read addr 1
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sigADDR = addr;
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sigOE = false; // enable outputs from RAM when reading
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// RAS falling
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sigRAS = false;
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wait(5, SC_NS);
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// CAS falling
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sigUCAS = false; sigLCAS = false;
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wait(5, SC_NS);
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// sample data bus (RAM should drive)
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sc_lv<16> read_lv = sigDATA.read();
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uint16_t read_val = (uint16_t)read_lv.to_uint64();
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std::cout << "READ val = 0x" << std::hex << read_val << " expected 0x" << write_val << std::dec << std::endl;
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// finish
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sc_stop();
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}
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};
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int sc_main(int argc, char* argv[])
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{
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Testbench tb("tb");
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sc_start();
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return 0;
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}
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