99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/*
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** Copyright (c) 1995, 3Dfx Interactive, Inc.
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** All Rights Reserved.
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**
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** This is UNPUBLISHED PROPRIETARY SOURCE CODE of 3Dfx Interactive, Inc.;
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** the contents of this file may not be disclosed to third parties, copied or
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** duplicated in any form, in whole or in part, without the prior written
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** permission of 3Dfx Interactive, Inc.
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**
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** RESTRICTED RIGHTS LEGEND:
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** Use, duplication or disclosure by the Government is subject to restrictions
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** as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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** and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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** successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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** rights reserved under the Copyright Laws of the United States.
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*/
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#ifndef __OEMINIT_H__
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#define __OEMINIT_H__
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#define OEMINIT_INVALID_BOARD_ID 0xdeadfeed
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#define OEMINIT_VERSION 0x10001
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#include "3dfx.h"
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#define FX_DLL_DEFINITION
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#include "fxdll.h"
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#include "sst1vid.h"
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#define FX_OEM_CONTROL_ACTIVATE 1
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#define FX_OEM_CONTROL_DEACTIVATE 2
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#define FX_OEM_TVOUT 1
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#define FX_OEM_SLIMASTER 2
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#define FX_OEM_SLISLAVE 3
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#define FX_OEM_FBI_CONFIG_SHIFT 8
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typedef enum {
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OEM_READ_ONLY,
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OEM_WRITE_ONLY,
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OEM_READ_WRITE
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} OemPciIOFlag;
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typedef struct {
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FxU32 regAddress;
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FxU32 sizeInBytes;
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OemPciIOFlag rwFlag;
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} OemPciRegister;
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typedef FxU32 (FX_CALL* PciConfigProc)(OemPciRegister, FxU32, FxU32 *);
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typedef struct {
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GrScreenResolution_t res;
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GrScreenRefresh_t refresh;
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FxU32 depth;
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FxU32 hSyncOn;
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FxU32 hSyncOff;
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FxU32 vSyncOn;
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FxU32 vSyncOff;
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FxU32 hBackPorch;
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FxU32 vBackPorch;
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FxU32 xDimension;
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FxU32 yDimension;
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float clkFreq16bpp;
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float clkFreq24bpp;
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} OemVideoTimingInfo;
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typedef struct {
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FxU32 version; /* Version for this structure */
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FxU32 vendorID; /* PCI Vendor ID field */
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FxU32 subvendorID; /* PCI sub Vendor ID field */
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FxU32 deviceID; /* PCI Device ID field */
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FxU32 boardID; /* Board ID: defined for Voodoo2 only!!! */
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FxU32 *linearAddress; /* address for primary board */
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FxU32 *slaveAddress; /* address for slave board */
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PciConfigProc fxoemPciWriteConfig;
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PciConfigProc fxoemPciReadConfig;
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OemVideoTimingInfo vid;
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FxU32 reserved[42];
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} OemInitInfo;
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitMapBoard(OemInitInfo *oem);
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FX_EXPORT FxI32 FX_CSTYLE fxoemGet(FxU32 pname, FxU32 plength, FxI32 *params);
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitVideoTiming(OemVideoTimingInfo *vid);
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FX_EXPORT FxU32 FX_CSTYLE fxoemInitSetVideo(OemInitInfo *oem);
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FX_EXPORT FxU32 FX_CSTYLE fxoemRestoreVideo(OemInitInfo *oem);
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FX_EXPORT FxU32 FX_CSTYLE fxoemControl(FxU32 mode);
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FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlP(OemInitInfo* oemInfo);
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FX_EXPORT FxU32 FX_CSTYLE fxoemSwapControlWrite(OemInitInfo* oemInfo,
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FxU32* writeBuffer);
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typedef FxU32 (FX_CALL* FxOemSwapControlP)(OemInitInfo* oemInfo);
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typedef FxU32 (FX_CALL* FxOemSwapControlWrite)(OemInitInfo* oemInfo,
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FxU32* writeBuffer);
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#endif __OEMINIT_H__
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