906 lines
34 KiB
C
906 lines
34 KiB
C
/*
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** THIS SOFTWARE IS SUBJECT TO COPYRIGHT PROTECTION AND IS OFFERED ONLY
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** PURSUANT TO THE 3DFX GLIDE GENERAL PUBLIC LICENSE. THERE IS NO RIGHT
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** TO USE THE GLIDE TRADEMARK WITHOUT PRIOR WRITTEN PERMISSION OF 3DFX
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** INTERACTIVE, INC. A COPY OF THIS LICENSE MAY BE OBTAINED FROM THE
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** DISTRIBUTOR OR BY CONTACTING 3DFX INTERACTIVE INC(info@3dfx.com).
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** THIS PROGRAM IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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** EXPRESSED OR IMPLIED. SEE THE 3DFX GLIDE GENERAL PUBLIC LICENSE FOR A
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** FULL TEXT OF THE NON-WARRANTY PROVISIONS.
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**
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** USE, DUPLICATION OR DISCLOSURE BY THE GOVERNMENT IS SUBJECT TO
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** RESTRICTIONS AS SET FORTH IN SUBDIVISION (C)(1)(II) OF THE RIGHTS IN
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** TECHNICAL DATA AND COMPUTER SOFTWARE CLAUSE AT DFARS 252.227-7013,
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** AND/OR IN SIMILAR OR SUCCESSOR CLAUSES IN THE FAR, DOD OR NASA FAR
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** SUPPLEMENT. UNPUBLISHED RIGHTS RESERVED UNDER THE COPYRIGHT LAWS OF
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** THE UNITED STATES.
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**
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** COPYRIGHT 3DFX INTERACTIVE, INC. 1999, ALL RIGHTS RESERVED
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**
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** $Revision$
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** $Date$
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**
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*/
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/*
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** Initialization code for SST-1 board.
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**
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** NOTE: This code must compiled with optimizations DISABLED!!
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**
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** The following environment variables can optionally be used to alter
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** functionality (A value of X is a "don't care"):
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**
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** Variable Value Description
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** -------- ----- -----------
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** SST_ARCADE X Allow special configs for arcade use
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** SST_BACKPORCH hex Specify value of backPorch video register
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** SST_BOARDS val Specify number of SST-1 boards in system
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** SST_DEBUGDAC X Print out debug information for DAC
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** reads and writes
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** SST_DIMENSIONS hex Specify value of videoDimensions register
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** SST_FASTMEM 1 Default. Enable fast memory timing
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** SST_FASTMEM 0 Disable fast memory timing
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** SST_FASTPCIRD X Enable fast PCI reads
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** SST_FBICFG hex Specify FBI configuration strapping bits
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** SST_FBIMEM_SIZE val Specify amount of frame buffer memory
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** SST_FT_CLK_DEL hex Fbi-to-Trex clock delay value
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** SST_GAMMA float Floating point value for gamma correction
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** SST_GRXCLK val 16 <= Frequency < 80 (50 is default)
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** SST_HSYNC hex Specify value of hSync video register
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** SST_IGNORE_INIT_GAMMA X Bypass sst1InitGamma call and return
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** SST_IGNORE_INIT_REGISTERS X Bypass sst1InitRegisters call and return
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** SST_IGNORE_INIT_VIDEO X Bypass sst1InitVideo call and return
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** SST_IGNORE_SLI_CHECK X Ignore checking for proper SLI install
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** SST_INITDEBUG X Enable debug output
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** SST_INITDEBUG_FILE file File to direct all debug output
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** SST_MEMFIFO 0 Disable FBI Memory FIFO
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** SST_MEMFIFO 1 Enable FBI Memory FIFO
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** SST_MEMFIFO_ENTRIES hex Set number of entries in memory fifo
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** SST_MEMFIFO_HWM hex Set memory fifo high water mark
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** SST_MEMFIFO_LFB 0 or 1 Specify LFB writes through Memory FIFO
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** SST_MEMFIFO_LWM hex Set memory fifo low water mark
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** SST_MEMFIFO_TEX 0 or 1 Specify Texture writes through Mem FIFO
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** SST_MEMOFFSET hex Specify value of memoffset video register
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** SST_NOCHECKHANG X Do not Check for FBI Hangs for texturing
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** SST_NODEVICEINFO X Ignore calls to sst1InitFillDeviceInfo()
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** SST_NOSHUTDOWN X Do not turn off monitor refresh on call
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** to sst1InitShutdown()
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** SST_PCIFIFO_LWM hex Set pci fifo low water mark
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** SST_PFT_CLK_DEL hex Preliminary Fbi-to-Trex clock delay value
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** SST_PTF0_CLK_DEL hex Prelim TMU2Fbi clock delay value (TMU #0)
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** SST_PTF1_CLK_DEL hex Prelim TMU2Fbi clock delay value (TMU #1)
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** SST_PTF2_CLK_DEL hex Prelim TMU2Fbi clock delay value (TMU #2)
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** SST_SLIDETECT 0 or 1 Specify Scanline Interleaving detection
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** SST_SLIM_VIN_CLKDEL hex Specify FBI internal video clock delay
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** (SLI Master)
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** SST_SLIM_VOUT_CLKDEL hex Specify FBI external video clock delay
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** (SLI Master)
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** SST_SLIS_VIN_CLKDEL hex Specify FBI internal video clock delay
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** (SLI Slave)
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** SST_SLIS_VOUT_CLKDEL hex Specify FBI external video clock delay
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** (SLI Slave)
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** SST_SCREENREFRESH 60 Select 60Hz monitor refresh rate
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** (overrides argument to sst1InitVideo)
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** SST_SCREENREFRESH 75 Select 75Hz monitor refresh rate
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** SST_SCREENREZ 512 Select 512x384 video resolution
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** (overrides argument to sst1InitVideo)
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** SST_SCREENREZ 640 Select 640x480 video resolution
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** SST_SCREENREZ 800 Select 800x600 video resolution
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** SST_SLOWPCIWR X Enable 1 wait-state PCI writes
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** SST_TEXMAP_DISABLE X Disable texture mapping
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** SST_TF0_CLK_DEL hex Trex-to-Fbi clock delay value (TMU #0)
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** SST_TF1_CLK_DEL hex Trex-to-Fbi clock delay value (TMU #1)
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** SST_TF2_CLK_DEL hex Trex-to-Fbi clock delay value (TMU #2)
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** SST_TF_FIFO_THRESH hex Set TREX-to-FBI FIFO threshold
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** SST_TILESINX hex Specify value of tilesInX video register
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** SST_TMUCFG hex Specify TMU configuration strapping bits
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** SST_TMUMEM X Enable accurate determination of TMU mem
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** SST_TMUMEM_SIZE val Specify amount of texture memory
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** SST_TREX0INIT0 hex Set trexInit0 register value - TMU #0
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** SST_TREX0INIT1 hex Set trexInit1 register value - TMU #0
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** SST_TREX1INIT0 hex Set trexInit0 register value - TMU #1
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** SST_TREX1INIT1 hex Set trexInit1 register value - TMU #1
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** SST_TREX2INIT0 hex Set trexInit0 register value - TMU #2
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** SST_TREX2INIT1 hex Set trexInit1 register value - TMU #2
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** SST_TRIPLE_BUFFER X Enable Triple Buffering
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** SST_VIN_CLKDEL hex Specify FBI internal video clock delay
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** SST_VOUT_CLKDEL hex Specify FBI external video clock delay
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** SST_VGA_PASS 0,1 Force VGA_PASS output to {0,1}
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** SST_VIDCLK2X val Video clock frequency (2x dot clock)
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** SST_VIDEO_24BPP 0 Select 16-bit video output
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** SST_VIDEO_24BPP 1 Select 24-bit video output
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** SST_VIDEO_DISABLE X Turn off Video/Monitor refresh in FBI
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** SST_VIDEO_FILTER_DISABLE X Disable video filtering
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** SST_VIDEO_FILTER_THRESHOLD hex Set video filtering threshold
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** SST_VIDEO_NOCLEAR X Do not clear buffers in sst1InitVideo()
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** SST_VIDEO_CLEARCOLOR hex Clear screen color
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** SST_VFIFO_THRESH 0-31 Select video fifo threshold
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** SST_VSYNC hex Specify value of vSync video register
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**
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** VOODOO_FILE name Filename used in place of "voodoo.ini"
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** VOODOO_PATH path Path used to locate "voodoo.ini" file
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**
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*/
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#pragma optimize ("",off)
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include <sst.h>
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#include <fxpci.h>
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#define SST1INIT_ALLOCATE /* Allocate variables in sst1init.h */
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#define FX_DLL_DEFINITION
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#include <fxdll.h>
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#include <sst1vid.h>
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#include <sst1init.h>
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#include "rcver.h"
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#ifdef __WIN32__
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#include <windows.h>
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#endif
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/*
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** sst1InitMapBoard():
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** Find and map SST-1 board into virtual memory
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**
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** Returns:
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** FxU32 pointer to base of SST-1 board if successful mapping occurs
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** FXFALSE if cannot map or find SST-1 board
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**
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*/
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FX_EXPORT FxU32 * FX_CSTYLE sst1InitMapBoard(FxU32 BoardNumber)
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{
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static FxU32 firstTime = 1;
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FxU32 sizeOfCard = 0x1000000; /* 16 MBytes of addr space for SST-1 */
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FxU32 *sst;
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volatile Sstregs *sstptr;
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FxU32 n, j;
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if(firstTime) {
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/* Find "voodoo.ini" file if it exists... */
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sst1InitUseVoodooFile = sst1InitVoodooFile();
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if(!(boardsInSystem = sst1InitNumBoardsInSystem()))
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return(NULL);
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}
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if(BoardNumber == 0) {
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INIT_PRINTF(("sst1Init Routines"));
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INIT_PRINTF(("sst1InitMapBoard(): BoardsInSystem = %d\n",
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boardsInSystem));
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/* Clear board info structure */
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sst1InitClearBoardInfo();
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}
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if(firstTime) {
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firstTime = 0;
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sst1InitClearBoardInfo();
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/* Map all boards in the system */
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/* Check that scanline interleaving is not enabled... */
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for(j=0; j<SST1INIT_MAX_BOARDS; j++) {
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FxU32 vendorID = _3DFX_PCI_ID; /* 3Dfx Vendor ID */
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FxU32 deviceID = 1; /* Find only sst1 boards */
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#ifndef DIRECTX
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sst = pciMapCardMulti(vendorID, deviceID, sizeOfCard,
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&sst1InitDeviceNumber, j, 0);
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#else
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sst = pciMapCardMulti(vendorID, deviceID, sizeOfCard,
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&sst1InitDeviceNumber, j, 0);
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#endif /* DIRECTX */
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if(sst) {
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sst1BoardInfo[j].virtAddr = sst;
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PCICFG_RD(PCI_BASE_ADDRESS_0, sst1BoardInfo[j].physAddr);
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sst1BoardInfo[j].deviceNumber = sst1InitDeviceNumber;
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sst1BoardInfo[j].numBoardInsystem = j;
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PCICFG_RD(PCI_REVISION_ID, sst1BoardInfo[j].fbiRevision);
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PCICFG_RD(PCI_DEVICE_ID, sst1BoardInfo[j].deviceID);
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PCICFG_RD(PCI_VENDOR_ID, sst1BoardInfo[j].vendorID);
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/* Enable Memory accesses to SST-1 */
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/* Must be set for PnP BIOS which do not enable memory mapped */
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/* accesses (sst1InitSliDetect reads memory mapped regs) */
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PCICFG_WR(PCI_COMMAND, SST_PCIMEM_ACCESS_EN);
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sstptr = (Sstregs *) sst;
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/* Check SLI not enabled... */
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if((IGET(sstptr->fbiInit1) & SST_EN_SCANLINE_INTERLEAVE) &&
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sst1InitSliDetect(sst)) {
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INIT_PRINTF(("sst1InitMapBoard(): Scanline Interleave detected at startup for board=%d\n", j));
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INIT_PRINTF((" System reboot required...\n"));
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return(NULL);
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}
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} else {
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FxU32 code = pciGetErrorCode();
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if (code == PCI_ERR_WRONGVXD) {
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#ifdef __WIN32__
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MessageBox(NULL, pciGetErrorString(), NULL, MB_OK);
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#endif /* __WIN32__ */
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exit(1);
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}
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sst1BoardInfo[j].virtAddr = (FxU32 *) NULL;
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sst1BoardInfo[j].physAddr = (FxU32) NULL;
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sst1BoardInfo[j].deviceNumber = 0xdead;
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sst1BoardInfo[j].numBoardInsystem = 0xdead;
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sst1BoardInfo[j].fbiRevision = 0xdead;
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sst1BoardInfo[j].deviceID = 0xdead;
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sst1BoardInfo[j].vendorID = 0xdead;
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}
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}
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}
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/* Max number of supported boards in system */
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if(BoardNumber > SST1INIT_MAX_BOARDS) return(NULL);
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if(!(sst = sst1BoardInfo[BoardNumber].virtAddr))
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return (NULL);
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INIT_PRINTF(("sst1InitMapBoard(): vAddr:0x%x pAddr:0x%x Dev:0x%x Board:%d\n",
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(FxU32) sst1BoardInfo[BoardNumber].virtAddr,
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(FxU32) sst1BoardInfo[BoardNumber].physAddr,
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(FxU32) sst1BoardInfo[BoardNumber].deviceNumber, BoardNumber));
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sstptr = (Sstregs *) sst;
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/* Default settings */
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if((IGET(sstptr->fbiInit3) & SST_FBI_VGA_PASS_POWERON) &&
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(sst1BoardInfo[BoardNumber].fbiRevision > 0)) {
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sst1BoardInfo[BoardNumber].vgaPassthruDisable = 0x0;
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sst1BoardInfo[BoardNumber].vgaPassthruEnable = SST_EN_VGA_PASSTHRU;
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sst1BoardInfo[BoardNumber].fbiRegulatorPresent = 0x1;
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} else {
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sst1BoardInfo[BoardNumber].vgaPassthruDisable = SST_EN_VGA_PASSTHRU;
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sst1BoardInfo[BoardNumber].vgaPassthruEnable = 0x0;
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sst1BoardInfo[BoardNumber].fbiRegulatorPresent = 0x0;
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}
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sst1BoardInfo[BoardNumber].fbiVideo16BPP = 0;
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if(GETENV(("SST_VGA_PASS"))) {
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INIT_PRINTF(("sst1InitMapBoard(): Using SST_VGA_PASS=%d\n",
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ATOI(GETENV(("SST_VGA_PASS")))));
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if(ATOI(GETENV(("SST_VGA_PASS")))) {
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sst1BoardInfo[BoardNumber].vgaPassthruEnable = SST_EN_VGA_PASSTHRU;
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sst1BoardInfo[BoardNumber].vgaPassthruDisable = 0x0;
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} else {
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sst1BoardInfo[BoardNumber].vgaPassthruDisable = SST_EN_VGA_PASSTHRU;
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sst1BoardInfo[BoardNumber].vgaPassthruEnable = 0x0;
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}
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}
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return(sst);
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}
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/*
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** sst1InitRegisters():
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** Initialize registers and memory and return to power-on state
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**
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** Returns:
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** FXTRUE if successfully initializes SST-1
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** FXFALSE if cannot initialize SST-1
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**
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*/
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FX_EXPORT FxBool FX_CSTYLE sst1InitRegisters(FxU32 *sstbase)
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{
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FxU32 n, tf_fifo_thresh;
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FxU32 ft_clk_del, tf0_clk_del, tf1_clk_del, tf2_clk_del;
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sst1ClkTimingStruct sstGrxClk;
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volatile Sstregs *sst = (Sstregs *) sstbase;
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if(!sst)
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return(FXFALSE);
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if(sst1InitCheckBoard(sstbase) == FXFALSE)
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return(FXFALSE);
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if(GETENV(("SST_IGNORE_INIT_REGISTERS"))) {
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INIT_PRINTF(("WARNING: Ignoring sst1InitRegisters()...\n"));
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sst1InitIdleFBINoNOP(sstbase);
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return(FXTRUE);
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}
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/* Disable video clock */
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PCICFG_WR(SST1_PCI_VCLK_DISABLE, 0x0);
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/* Enable writes to the FBIINIT registers */
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/* Do not allow writes into the pci fifo until everything is reset */
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PCICFG_WR(SST1_PCI_INIT_ENABLE, SST_INITWR_EN);
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/* Reset Snoop registers to default values */
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#if 0
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PCICFG_WR(SST1_PCI_BUS_SNOOP0, SST_PCI_BUS_SNOOP_DEFAULT);
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PCICFG_WR(SST1_PCI_BUS_SNOOP1, SST_PCI_BUS_SNOOP_DEFAULT);
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#else
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PCICFG_WR(SST1_PCI_BUS_SNOOP_0, SST_PCI_BUS_SNOOP_DEFAULT);
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PCICFG_WR(SST1_PCI_BUS_SNOOP_1, SST_PCI_BUS_SNOOP_DEFAULT);
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#endif
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sst1InitReturnStatus(sstbase); /* Stall - can't call IdleFbi because */
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/* FBI could be hung at this stage */
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sst1InitReturnStatus(sstbase);
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sst1InitReturnStatus(sstbase);
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/* Adjust Fbi-to-Trex clock delay value */
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/* Adjust Trex-to-Fbi FIFO */
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if(GETENV(("SST_TF_FIFO_THRESH")))
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SSCANF(GETENV(("SST_TF_FIFO_THRESH")), "%i", &tf_fifo_thresh);
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else
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tf_fifo_thresh = 0x8;
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INIT_PRINTF(("sst1InitRegisters(): Setting TREX-to-FBI FIFO THRESHOLD to 0x%x...\n",
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tf_fifo_thresh));
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/* Set ft_clk_del for 16 MHz bringup */
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if(sst1CurrentBoard->fbiRevision == 2)
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/* .5 micron */
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ft_clk_del = 0x8; /* Okay for 16 MHz startup... */
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else
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/* .6 micron */
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ft_clk_del = 0xa; /* Okay for 16 MHz startup... */
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if(GETENV(("SST_PFT_CLK_DEL")))
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SSCANF(GETENV(("SST_PFT_CLK_DEL")), "%i", &ft_clk_del);
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INIT_PRINTF(("sst1InitRegisters(): Setting PRELIM FT-CLK delay to 0x%x...\n", ft_clk_del));
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ISET(sst->fbiInit3,
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(SST_FBIINIT3_DEFAULT & ~(SST_FT_CLK_DEL_ADJ | SST_TF_FIFO_THRESH)) |
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(ft_clk_del << SST_FT_CLK_DEL_ADJ_SHIFT) |
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(tf_fifo_thresh << SST_TF_FIFO_THRESH_SHIFT));
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/* Wait for Fbi-to-Trex clock delay value to propogate */
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sst1InitReturnStatus(sstbase); /* Stall - can't call IdleFbi because */
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/* FBI could be hung at this stage */
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sst1InitReturnStatus(sstbase);
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sst1InitReturnStatus(sstbase);
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/* Reset graphics and video units */
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/* Must reset video unit before graphics unit, otherwise video unit could */
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/* potentially hang waiting for the graphics unit to respond */
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ISET(sst->fbiInit1, IGET(sst->fbiInit1) | SST_VIDEO_RESET);
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/* don't wait for idle b/c grx could be hung */
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sst1InitReturnStatus(sstbase);
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sst1InitReturnStatus(sstbase);
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sst1InitReturnStatus(sstbase);
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ISET(sst->fbiInit0,
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IGET(sst->fbiInit0) | (SST_GRX_RESET | SST_PCI_FIFO_RESET));
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sst1InitIdleFBINoNOP(sstbase);
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/* Unreset PCI FIFO... */
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ISET(sst->fbiInit0, IGET(sst->fbiInit0) & ~SST_PCI_FIFO_RESET);
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sst1InitIdleFBINoNOP(sstbase);
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/* Unreset graphics subsystem */
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/* THIS MUST BE PRESENT OTHERWISE THE PCI FIFO WILL NEVER DRAIN! */
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ISET(sst->fbiInit0, IGET(sst->fbiInit0) & ~SST_GRX_RESET);
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sst1InitIdleFBINoNOP(sstbase);
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/* Reset all FBI and TREX Init registers */
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ISET(sst->fbiInit0, SST_FBIINIT0_DEFAULT);
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ISET(sst->fbiInit1, SST_FBIINIT1_DEFAULT);
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ISET(sst->fbiInit2, SST_FBIINIT2_DEFAULT);
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ISET(sst->fbiInit3,
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(SST_FBIINIT3_DEFAULT & ~(SST_FT_CLK_DEL_ADJ | SST_TF_FIFO_THRESH)) |
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(ft_clk_del << SST_FT_CLK_DEL_ADJ_SHIFT) |
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(tf_fifo_thresh << SST_TF_FIFO_THRESH_SHIFT));
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ISET(sst->fbiInit4, SST_FBIINIT4_DEFAULT);
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sst1InitIdleFBINoNOP(sstbase); /* Wait until init regs are reset */
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/* Enable writes to the FBIINIT registers and allow pushes onto PCI FIFO */
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PCICFG_WR(SST1_PCI_INIT_ENABLE, (SST_INITWR_EN | SST_PCI_FIFOWR_EN));
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/* Determine DAC Type */
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if(sst1InitDacDetect(sstbase) == FXFALSE) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Could not detect DAC...\n"));
|
|
return(FXFALSE);
|
|
}
|
|
|
|
/* set TREX0 init values */
|
|
if(GETENV(("SST_TREX0INIT0"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX0INIT0 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX0INIT0")), "%i",
|
|
&sst1CurrentBoard->tmuInit0[0]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit0[0] = SST_TREX0INIT0_DEFAULT;
|
|
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX0INIT0=0x%x\n",
|
|
sst1CurrentBoard->tmuInit0[0]));
|
|
if(GETENV(("SST_TREX0INIT1"))) {
|
|
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX0INIT1 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX0INIT1")), "%i",
|
|
&sst1CurrentBoard->tmuInit1[0]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit1[0] = SST_TREX0INIT1_DEFAULT;
|
|
if(GETENV(("SST_PTF0_CLK_DEL"))) {
|
|
SSCANF(GETENV(("SST_PTF0_CLK_DEL")), "%i", &tf0_clk_del);
|
|
sst1CurrentBoard->tmuInit1[0] = (sst1CurrentBoard->tmuInit1[0] &
|
|
~SST_TEX_TF_CLK_DEL_ADJ) |
|
|
(tf0_clk_del<<SST_TEX_TF_CLK_DEL_ADJ_SHIFT);
|
|
}
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX0INIT1=0x%x\n",
|
|
sst1CurrentBoard->tmuInit1[0]));
|
|
|
|
ISET(SST_TREX(sst,0)->trexInit0, sst1CurrentBoard->tmuInit0[0]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
ISET(SST_TREX(sst,0)->trexInit1, sst1CurrentBoard->tmuInit1[0]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* set TREX1 init values */
|
|
if(GETENV(("SST_TREX1INIT0"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX1INIT0 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX1INIT0")), "%i",
|
|
&sst1CurrentBoard->tmuInit0[1]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit0[1] = SST_TREX1INIT0_DEFAULT;
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX1INIT0=0x%x\n",
|
|
sst1CurrentBoard->tmuInit0[1]));
|
|
if(GETENV(("SST_TREX1INIT1"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX1INIT1 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX1INIT1")), "%i",
|
|
&sst1CurrentBoard->tmuInit1[1]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit1[1] = SST_TREX1INIT1_DEFAULT;
|
|
if(GETENV(("SST_PTF1_CLK_DEL"))) {
|
|
SSCANF(GETENV(("SST_PTF1_CLK_DEL")), "%i", &tf1_clk_del);
|
|
sst1CurrentBoard->tmuInit1[1] = (sst1CurrentBoard->tmuInit1[1] &
|
|
~SST_TEX_TF_CLK_DEL_ADJ) |
|
|
(tf1_clk_del<<SST_TEX_TF_CLK_DEL_ADJ_SHIFT);
|
|
}
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX1INIT1=0x%x\n",
|
|
sst1CurrentBoard->tmuInit1[1]));
|
|
|
|
ISET(SST_TREX(sst,1)->trexInit0, sst1CurrentBoard->tmuInit0[1]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
ISET(SST_TREX(sst,1)->trexInit1, sst1CurrentBoard->tmuInit1[1]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* set TREX2 init values */
|
|
if(GETENV(("SST_TREX2INIT0"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX2INIT0 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX2INIT0")), "%i",
|
|
&sst1CurrentBoard->tmuInit0[2]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit0[2] = SST_TREX2INIT0_DEFAULT;
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX2INIT0=0x%x\n",
|
|
sst1CurrentBoard->tmuInit0[2]));
|
|
if(GETENV(("SST_TREX2INIT1"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Using SST_TREX2INIT1 environment variable\n"));
|
|
SSCANF(GETENV(("SST_TREX2INIT1")), "%i",
|
|
&sst1CurrentBoard->tmuInit1[2]);
|
|
} else
|
|
sst1CurrentBoard->tmuInit1[2] = SST_TREX2INIT1_DEFAULT;
|
|
if(GETENV(("SST_PTF2_CLK_DEL"))) {
|
|
SSCANF(GETENV(("SST_PTF2_CLK_DEL")), "%i", &tf2_clk_del);
|
|
sst1CurrentBoard->tmuInit1[2] = (sst1CurrentBoard->tmuInit1[2] &
|
|
~SST_TEX_TF_CLK_DEL_ADJ) |
|
|
(tf2_clk_del<<SST_TEX_TF_CLK_DEL_ADJ_SHIFT);
|
|
}
|
|
INIT_PRINTF(("sst1InitRegisters(): Storing TREX2INIT1=0x%x\n",
|
|
sst1CurrentBoard->tmuInit1[2]));
|
|
|
|
ISET(SST_TREX(sst,2)->trexInit0, sst1CurrentBoard->tmuInit0[2]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
ISET(SST_TREX(sst,2)->trexInit1, sst1CurrentBoard->tmuInit1[2]);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* Set clock at 16 MHz to sense TREX configuration... */
|
|
if(sst1InitComputeClkParams((float) 16.0, &sstGrxClk) == FXFALSE)
|
|
return(FXFALSE);
|
|
if(sst1InitSetGrxClk(sstbase, &sstGrxClk) == FXFALSE)
|
|
return(FXFALSE);
|
|
|
|
/* Set PCI wait-states */
|
|
if(GETENV(("SST_SLOWPCIWR"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Setting up SLOW PCI Writes...\n"));
|
|
ISET(sst->fbiInit1, IGET(sst->fbiInit1) | SST_PCI_WRWS_1);
|
|
} else
|
|
ISET(sst->fbiInit1, IGET(sst->fbiInit1) & ~SST_PCI_WRWS_1);
|
|
|
|
if(GETENV(("SST_FASTPCIRD"))) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Setting up FAST PCI Reads...\n"));
|
|
ISET(sst->fbiInit4, IGET(sst->fbiInit4) & ~SST_PCI_RDWS_2);
|
|
}
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* Enable Linear frame buffer reads */
|
|
ISET(sst->fbiInit1, IGET(sst->fbiInit1) | SST_LFB_READ_EN);
|
|
|
|
/* Swapbuffer algorithm is based on VSync initially */
|
|
ISET(sst->fbiInit2, (IGET(sst->fbiInit2) & ~SST_SWAP_ALGORITHM) |
|
|
SST_SWAP_VSYNC);
|
|
|
|
/* Enable LFB read-aheads */
|
|
ISET(sst->fbiInit4, IGET(sst->fbiInit4) | SST_EN_LFB_RDAHEAD);
|
|
|
|
/* Enable triangle alternate register mapping */
|
|
ISET(sst->fbiInit3, IGET(sst->fbiInit3) | SST_ALT_REGMAPPING);
|
|
|
|
#if 0
|
|
/* Enable Endian Byte Swapping */
|
|
/* Do not enable byte swapping due to potential bug in FBI... */
|
|
ISET(sst->fbiInit0, IGET(sst->fbiInit0) | SST_EN_ENDIAN_SWAPPING);
|
|
#endif
|
|
|
|
/* Setup DRAM Refresh */
|
|
ISET(sst->fbiInit2, (IGET(sst->fbiInit2) & ~SST_DRAM_REFRESH_CNTR) |
|
|
SST_DRAM_REFRESH_16MS);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
ISET(sst->fbiInit2, IGET(sst->fbiInit2) | SST_EN_DRAM_REFRESH);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
if(GETENV(("SST_FASTMEM")))
|
|
n = ATOI(GETENV(("SST_FASTMEM")));
|
|
else
|
|
n = 1;
|
|
|
|
if(n) {
|
|
INIT_PRINTF(("sst1InitRegisters(): Setting up FAST DRAM Configuration\n"));
|
|
ISET(sst->fbiInit2, IGET(sst->fbiInit2) | (SST_EN_FAST_RAS_READ |
|
|
SST_EN_DRAM_RD_AHEAD_FIFO | SST_EN_FAST_RD_AHEAD_WR));
|
|
} else
|
|
ISET(sst->fbiInit1, IGET(sst->fbiInit1) | SST_DISEN_RD_AHEAD_WR_RD);
|
|
|
|
/* Return all other registers to their power-on state */
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
sst1InitSetResolution(sstbase, &SST_VREZ_640X480_60, 0);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* Get DRAMs up and running (refresh is already enabled)... */
|
|
ISET(sst->c1, 0x0);
|
|
ISET(sst->c0, 0x0);
|
|
ISET(sst->zaColor, 0x0);
|
|
ISET(sst->clipLeftRight, 100); /* draw into 50x50 area */
|
|
ISET(sst->clipBottomTop, 100);
|
|
ISET(sst->fbzMode, SST_RGBWRMASK | SST_ZAWRMASK);
|
|
ISET(sst->fastfillCMD, 0x0); /* Frontbuffer & Z/A */
|
|
ISET(sst->nopCMD, 0x1); /* Clear fbistat registers after clearing screen */
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
sst1InitRenderingRegisters(sstbase);
|
|
if(sst1InitFillDeviceInfo(sstbase, sst1CurrentBoard) == FXFALSE) {
|
|
INIT_PRINTF(("sst1InitRegisters(): ERROR filling DeviceInfo...\n"));
|
|
return(FXFALSE);
|
|
}
|
|
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
sst1InitRenderingRegisters(sstbase);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
|
|
/* LFB writes stored in memory FIFO? */
|
|
if(GETENV(("SST_MEMFIFO_LFB")))
|
|
n = ATOI(GETENV(("SST_MEMFIFO_LFB")));
|
|
else
|
|
n = 1;
|
|
if(n) {
|
|
INIT_PRINTF(("sst1InitRegisters(): LFB Writes go through memory FIFO...\n"));
|
|
ISET(sst->fbiInit0, IGET(sst->fbiInit0) | SST_EN_LFB_MEMFIFO);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
}
|
|
|
|
/* Texture memory writes stored in memory FIFO? */
|
|
if(GETENV(("SST_MEMFIFO_TEX")))
|
|
n = ATOI(GETENV(("SST_MEMFIFO_TEX")));
|
|
else
|
|
n = 1;
|
|
if(n) {
|
|
INIT_PRINTF(("sst1InitRegisters(): TEXTURE Writes go through memory FIFO...\n"));
|
|
ISET(sst->fbiInit0, IGET(sst->fbiInit0) | SST_EN_TEX_MEMFIFO);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
}
|
|
|
|
ISET(sst->vRetrace, 0x0);
|
|
ISET(sst->backPorch, 0x0);
|
|
ISET(sst->videoDimensions, 0x0);
|
|
ISET(sst->hSync, 0x0);
|
|
ISET(sst->vSync, 0x0);
|
|
ISET(sst->videoFilterRgbThreshold, 0x0);
|
|
|
|
sst1InitIdleFBINoNOP(sstbase); /* Wait until init regs are reset */
|
|
|
|
if(GETENV(("SST_TEXMAP_DISABLE"))) {
|
|
INIT_PRINTF(("sst1InitRegisters() WARNING: Disabling texture mapping\n"));
|
|
ISET(sst->fbiInit3, IGET(sst->fbiInit3) | SST_TEXMAP_DISABLE);
|
|
sst1InitIdleFBINoNOP(sstbase);
|
|
}
|
|
INIT_PRINTF(("sst1InitRegisters(): exiting with status %d...\n", FXTRUE));
|
|
return(FXTRUE);
|
|
}
|
|
|
|
FX_EXPORT void FX_CSTYLE sst1InitRenderingRegisters(FxU32 *sstbase)
|
|
{
|
|
FxU32 i;
|
|
volatile Sstregs *sst = (Sstregs *) sstbase;
|
|
|
|
ISET(sst->vA.x, 0x0); ISET(sst->vA.y, 0x0);
|
|
ISET(sst->vB.x, 0x0); ISET(sst->vB.y, 0x0);
|
|
ISET(sst->vC.x, 0x0); ISET(sst->vC.y, 0x0);
|
|
|
|
ISET(sst->r, 0x0); ISET(sst->g, 0x0);
|
|
ISET(sst->b, 0x0); ISET(sst->z, 0x0);
|
|
ISET(sst->a, 0x0); ISET(sst->s, 0x0);
|
|
ISET(sst->t, 0x0); ISET(sst->w, 0x0);
|
|
|
|
ISET(sst->drdx, 0x0); ISET(sst->dgdx, 0x0);
|
|
ISET(sst->dbdx, 0x0); ISET(sst->dzdx, 0x0);
|
|
ISET(sst->dadx, 0x0); ISET(sst->dsdx, 0x0);
|
|
ISET(sst->dtdx, 0x0); ISET(sst->dwdx, 0x0);
|
|
|
|
ISET(sst->drdy, 0x0); ISET(sst->dgdy, 0x0);
|
|
ISET(sst->dbdy, 0x0); ISET(sst->dzdy, 0x0);
|
|
ISET(sst->dady, 0x0); ISET(sst->dsdy, 0x0);
|
|
ISET(sst->dtdy, 0x0); ISET(sst->dwdy, 0x0);
|
|
|
|
ISET(sst->fbzColorPath, 0x0);
|
|
ISET(sst->fogMode, 0x0);
|
|
ISET(sst->alphaMode, 0x0);
|
|
ISET(sst->fbzMode, 0x0);
|
|
ISET(sst->lfbMode, 0x0);
|
|
ISET(sst->clipLeftRight, 0x0);
|
|
ISET(sst->clipBottomTop, 0x0);
|
|
|
|
ISET(sst->fogColor, 0x0);
|
|
ISET(sst->zaColor, 0x0);
|
|
ISET(sst->chromaKey, 0x0);
|
|
ISET(sst->stipple, 0x0);
|
|
ISET(sst->c0, 0x0);
|
|
ISET(sst->c1, 0x0);
|
|
|
|
ISET(sst->nopCMD, 0x1); /* Clear fbistat registers */
|
|
|
|
for(i=0; i<32; i++)
|
|
ISET(sst->fogTable[i], 0x0);
|
|
|
|
/* clear TMU registers */
|
|
ISET(sst->textureMode, 0x0);
|
|
ISET(sst->tLOD, 0x0);
|
|
ISET(sst->tDetail, 0x0);
|
|
ISET(sst->texBaseAddr, 0x0);
|
|
ISET(sst->texBaseAddr1, 0x0);
|
|
ISET(sst->texBaseAddr2, 0x0);
|
|
ISET(sst->texBaseAddr38, 0x0);
|
|
|
|
for(i=0; i<12; i++) {
|
|
ISET(sst->nccTable0[i], 0x0);
|
|
ISET(sst->nccTable1[i], 0x0);
|
|
}
|
|
sst1InitIdle(sstbase);
|
|
}
|
|
|
|
/*
|
|
** sst1InitShutdown():
|
|
** Shutdown SST-1
|
|
** Resets state of VGA_PASS to return monitor control back to the VGA
|
|
** Powers-down the DAC
|
|
** Resets the graphics clock in FBI to conserve power
|
|
**
|
|
** Returns:
|
|
** FXTRUE if successfully shuts down SST-1
|
|
** FXFALSE if cannot shut down the SST-1
|
|
**
|
|
*/
|
|
FX_EXPORT FxBool FX_CSTYLE sst1InitShutdown(FxU32 *sstbase)
|
|
{
|
|
volatile Sstregs *sstMaster = (Sstregs *) sstbase;
|
|
volatile Sstregs *sstSlave = (Sstregs *) sst1InitSliSlaveVirtAddr;
|
|
volatile Sstregs *sstPtr;
|
|
FxU32 n;
|
|
FxU32 SliEnable = sst1InitSliEnabled;
|
|
sst1ClkTimingStruct sstGrxClk;
|
|
|
|
if(!sstbase)
|
|
return(FXFALSE);
|
|
|
|
/* Wait for the SST-1 to finish rendering... */
|
|
sst1InitIdle(sstbase);
|
|
|
|
if(sst1InitSliEnabled) {
|
|
if(sst1InitShutdownSli(sstbase) == FXFALSE)
|
|
return(FXFALSE);
|
|
}
|
|
#ifdef __DOS32__
|
|
/*
|
|
* HACK alert. -MS
|
|
*
|
|
* There's a pciClose(), but nobody calls it. This is needed by the
|
|
* DOS DPMI services to close fxmemmap.vxd.
|
|
*
|
|
* We need to move this to the "appropriate" place, wherever that may be.
|
|
*/
|
|
pciClose();
|
|
#endif
|
|
|
|
if(GETENV(("SST_NOSHUTDOWN")))
|
|
INIT_PRINTF(("sst1InitShutdown(): Bypassing shutdown with SST_NOSHUTDOWN\n", n));
|
|
|
|
n = 0;
|
|
while(!GETENV(("SST_NOSHUTDOWN"))) {
|
|
if(!n)
|
|
sstPtr = sstMaster;
|
|
else
|
|
sstPtr = sstSlave;
|
|
|
|
if(sst1InitCheckBoard((FxU32 *) sstPtr) == FXFALSE)
|
|
return(FXFALSE);
|
|
|
|
INIT_PRINTF(("sst1InitShutdown(): Shutting down SST-1 #%d...\n", n));
|
|
|
|
/* Reset video unit to guarantee no contentions on the memory bus */
|
|
/* Blank DAC so VGA Passthru works properly */
|
|
ISET(sstPtr->fbiInit1,
|
|
IGET(sstPtr->fbiInit1) | (SST_VIDEO_RESET | SST_VIDEO_BLANK_EN));
|
|
/* Turn off dram refresh to guarantee no contentions on the
|
|
memory bus */
|
|
ISET(sstPtr->fbiInit2, IGET(sstPtr->fbiInit2) & ~SST_EN_DRAM_REFRESH);
|
|
|
|
/* Reset graphics subsystem */
|
|
ISET(sstPtr->fbiInit0,
|
|
IGET(sstPtr->fbiInit0) | (SST_GRX_RESET | SST_PCI_FIFO_RESET));
|
|
sst1InitIdleFBINoNOP((FxU32 *) sstPtr);
|
|
ISET(sstPtr->fbiInit0, IGET(sstPtr->fbiInit0) & ~SST_PCI_FIFO_RESET);
|
|
sst1InitIdleFBINoNOP((FxU32 *) sstPtr);
|
|
ISET(sstPtr->fbiInit0, IGET(sstPtr->fbiInit0) & ~SST_GRX_RESET);
|
|
sst1InitIdleFBINoNOP((FxU32 *) sstPtr);
|
|
|
|
/* Turnaround VGA_PASS to allow VGA monitor */
|
|
sst1InitVgaPassCtrl((FxU32 *) sstPtr, 1);
|
|
|
|
sst1InitIdleFBINoNOP((FxU32 *) sstPtr);
|
|
|
|
/* Set clock at 30 MHz to reduce power consumption... */
|
|
sst1InitComputeClkParams((float) 30.0, &sstGrxClk);
|
|
if(sst1InitSetGrxClk((FxU32 *) sstPtr, &sstGrxClk) == FXFALSE)
|
|
return(FXFALSE);
|
|
sst1CurrentBoard->initGrxClkDone = 0;
|
|
|
|
if((++n > 1) || !SliEnable)
|
|
break;
|
|
}
|
|
sst1InitIdle(sstbase);
|
|
INIT_PRINTF(("sst1InitShutdown(): Returning with status %d...\n", FXTRUE));
|
|
#ifdef INIT_OUTPUT
|
|
if ( sst1InitMsgFile != stdout && sst1InitMsgFile )
|
|
fclose(sst1InitMsgFile);
|
|
#endif
|
|
return(FXTRUE);
|
|
}
|
|
|
|
/*
|
|
** sst1InitCheckBoard():
|
|
** Set internal global variables for multiple SST-1 support
|
|
**
|
|
*/
|
|
FX_EXPORT FxBool FX_CSTYLE sst1InitCheckBoard(FxU32 *sstbase)
|
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{
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FxU32 n;
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FxBool return_val = FXFALSE;
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for(n=0; n<boardsInSystem; n++) {
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if(sst1BoardInfo[n].virtAddr == sstbase) {
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sst1InitDeviceNumber = sst1BoardInfo[n].deviceNumber;
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sst1CurrentBoard = &sst1BoardInfo[n];
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return_val = FXTRUE;
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n = boardsInSystem;
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}
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}
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return(return_val);
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}
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/*
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** sst1InitGetBaseAddr():
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** Return virtual base address to hardware
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** Returns NULL if board requested has not been mapped
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**
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*/
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FX_EXPORT FxU32 * FX_CSTYLE sst1InitGetBaseAddr(FxU32 boardNum)
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{
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return(sst1BoardInfo[boardNum].virtAddr);
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}
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/*
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** sst1InitClearBoardInfo():
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** Clear board configuration information
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**
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*/
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void sst1InitClearBoardInfo(void)
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{
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FxU32 n, j;
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for(n=0; n<SST1INIT_MAX_BOARDS; n++) {
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//sst1BoardInfo[n].virtAddr = (FxU32 *) NULL;
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//sst1BoardInfo[n].physAddr = (FxU32) NULL;
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//sst1BoardInfo[n].deviceNumber = 0xdead;
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//sst1BoardInfo[n].vendorID = 0xdead;
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//sst1BoardInfo[n].deviceID = 0xdead;
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//sst1BoardInfo[n].fbiRevision = 0xdead;
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sst1BoardInfo[n].fbiBoardID = 0xdead;
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sst1BoardInfo[n].fbiVideo16BPP = 0xdead;
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sst1BoardInfo[n].fbiVideoWidth = 0xdead;
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sst1BoardInfo[n].fbiVideoHeight = 0xdead;
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sst1BoardInfo[n].fbiVideoRefresh = 0xdead;
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sst1BoardInfo[n].fbiMemoryFifoEn = 0x0;
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sst1BoardInfo[n].sstSliDetect = 0;
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sst1BoardInfo[n].tmuRevision = 0xdead;
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sst1BoardInfo[n].numberTmus = 0xdead;
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sst1BoardInfo[n].tmuConfig = 0xdead;
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sst1BoardInfo[n].fbiMemSize = 0x0;
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for(j=0; j<MAX_NUM_TMUS; j++) {
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sst1BoardInfo[n].tmuMemSize[j] = 0x0;
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sst1BoardInfo[n].tmuInit0[j] = 0xdead;
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sst1BoardInfo[n].tmuInit1[j] = 0xdead;
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}
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sst1BoardInfo[n].initGrxClkDone = 0;
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sst1BoardInfo[n].vgaPassthruDisable = 0;
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sst1BoardInfo[n].vgaPassthruEnable = 0;
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sst1BoardInfo[n].fbiDacType = 0xdead;
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sst1BoardInfo[n].memFifoStatusLwm = 0xdead;
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//sst1BoardInfo[n].numBoardInsystem = 0xdead;
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sst1BoardInfo[n].grxClkFreq = 0xdead;
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sst1BoardInfo[n].fbiMemSpeed = 50;
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sst1BoardInfo[n].tmuMemSpeed = 50;
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sst1BoardInfo[n].tmuClkFixed = 0;
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sst1BoardInfo[n].fbiRegulatorPresent = 0;
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sst1BoardInfo[n].fbiTripleBufferingEnabled = FXFALSE;
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}
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}
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/*
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** sst1InitNumBoardsInSystem():
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** Returns the number of SST-1 boards in the system
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**
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*/
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FX_ENTRY FxU32 FX_CSTYLE sst1InitNumBoardsInSystem(void)
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{
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FxU32 vendorID = _3DFX_PCI_ID; /* 3Dfx Vendor ID */
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FxU32 deviceID = 1; /* Find only sst1 boards */
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FxU32 numBoards, j, n;
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if(GETENV(("SST_BOARDS")))
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numBoards = ATOI(GETENV(("SST_BOARDS")));
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else {
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numBoards = 0;
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for(j=0; j<SST1INIT_MAX_BOARDS; j++) {
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if(pciFindCardMulti(vendorID, deviceID, &n, j))
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numBoards++;
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}
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}
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return(numBoards);
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}
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static FxU32
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mtrr;
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/*
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** sst1InitCachingOn
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**
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** Sets up memory caching on P6 systems.
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**
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*/
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FX_EXPORT void FX_CSTYLE
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sst1InitCachingOn(void)
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{
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FxU32
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physAddr;
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FxBool
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res;
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/* Turn on Write combining for wrap 1-n */
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pciGetConfigData(PCI_BASE_ADDRESS_0, sst1InitDeviceNumber, &physAddr);
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/* For some reason, there sometimes is a 008 at the end of the
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physical address, so mask that puppy RTF out */
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physAddr &= 0xfffff000;
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/* Set up USWC MTRR */
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res = pciFindMTRRMatch(physAddr, 0x1000000,
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PciMemTypeWriteCombining, &mtrr);
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if (!res)
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res = pciFindFreeMTRR(&mtrr);
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else
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return; /* It's already there. We're done. */
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if (res)
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pciSetMTRR(mtrr, physAddr, 0x1000000, PciMemTypeWriteCombining);
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} /* sst1InitSetCacheType */
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#pragma optimize ("",on)
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