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h5,dos_mode.c,lin_mode.c: made buildVideoModeData and setVideoModeSlave static.

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whitespace tidy-up.
This commit is contained in:
sezero
2018-08-08 23:55:32 +03:00
parent 12d926449a
commit 43291704cb
3 changed files with 163 additions and 172 deletions
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4
glide3x/h3/minihwc/dos_mode.c
View File

@@ -55,7 +55,6 @@
**
** 2 6/25/98 7:40p Dow
** Made it compile
**
*/
#include <string.h>
@@ -135,13 +134,12 @@ setVideoMode( unsigned long dummy, int xres, int yres, int refresh, void *hmon )
}
}
r.w.ax = 0x4f02;
r.w.bx = mode;
GDBG_INFO(80, "Setting mode 0x%x, 0x%x\n", r.w.ax, r.w.bx);
/* Do VGA Magic */
/* Do VGA Magic */
int386(0x10, &r, &rOut);
/* XXXTACO!! - We should check the return value */

34
glide3x/h5/minihwc/dos_mode.c
View File

@@ -46,7 +46,6 @@
**
** 2 6/25/98 7:40p Dow
** Made it compile
**
*/
#include <string.h>
@@ -147,13 +146,12 @@ setVideoMode( void *hwnd,
}
}
r.w.ax = 0x4f02;
r.w.bx = mode;
GDBG_INFO(80, "Setting mode 0x%x, 0x%x\n", r.w.ax, r.w.bx);
/* Do VGA Magic */
/* Do VGA Magic */
int386(0x10, &r, &rOut);
/* XXXTACO!! - We should check the return value */
@@ -193,11 +191,7 @@ FxBool checkResolutions (FxBool *supportedByResolution, FxU32 stride, void *hmon
}
#ifdef __WATCOMC__
#include "h3cini~1.h"
#else
#include "h3cinitdd.h"
#endif
#define CFG_READ(_chip, _offset) \
hwcReadConfigRegister(bInfo, _chip, offsetof(SstPCIConfigRegs, _offset))
@@ -384,13 +378,13 @@ initSlave(hwcBoardInfo *bInfo, FxU32 chipNum)
cmdStatus |= 1;
CFG_WRITE(0, status_command, cmdStatus);
{
{
FxU32 status, vgaInit0, vgaInit1;
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, status, status);
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, vgaInit0, vgaInit0);
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, vgaInit1, vgaInit1);
LOG((dbg,"initSlave(%d) done. slave status: %08lx vgaInit0: %08lx vgaInit1: %08lx\n",chipNum, status, vgaInit0, vgaInit1));
}
}
}
static FxU8 vgaattr[] = {0x00, 0x00, 0x00, 0x00, 0x00,
@@ -432,7 +426,7 @@ static FxU16 modeData[21] =
ISET8PHYS(0x0d4, _srcindex); \
modeData[_dstindex] = IGET8PHYS(0x0d5);
void
static void
buildVideoModeData(hwcBoardInfo *bInfo)
{
/* Snarf all VGA data we need from the master */
@@ -481,7 +475,7 @@ buildVideoModeData(hwcBoardInfo *bInfo)
}
}
void
static void
setVideoModeSlave(
FxU32 regBase) // regBase of the slave
{
@@ -840,7 +834,7 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
} else if(!sliEnable && aaEnable) {
/* SLI disabled, AA enabled */
CFG_WRITE(chipNum, cfgSliLfbCtrl, 0);
} else {
} else {
/* SLI enabled, AA enabled, 4 sample AA enabled */
sliRenderMask = ((numChips >> 1) - 1) << sliBandHeightLog2;
sliCompareMask = (chipNum >> 1) << sliBandHeightLog2;
@@ -1154,9 +1148,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0x00);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else if(chipNum == 1 || chipNum == 3) {
/* Second and fourth chips */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1171,9 +1165,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0xff);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else {
/* Third chip */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1203,9 +1197,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0x00);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else if(chipNum == 1 || chipNum == 3) {
/* Second and fourth chips */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1221,9 +1215,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0xff);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else {
/* Third chip */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |

27
glide3x/h5/minihwc/lin_mode.c
View File

@@ -416,13 +416,13 @@ initSlave(hwcBoardInfo *bInfo, FxU32 chipNum)
cmdStatus |= 1;
CFG_WRITE(0, status_command, cmdStatus);
{
{
FxU32 status, vgaInit0, vgaInit1;
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, status, status);
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, vgaInit0, vgaInit0);
HWC_IO_LOAD_SLAVE(chipNum, bInfo->regInfo, vgaInit1, vgaInit1);
LOG((dbg,"initSlave(%d) done. slave status: %08lx vgaInit0: %08lx vgaInit1: %08lx\n",chipNum, status, vgaInit0, vgaInit1));
}
}
}
static FxU8 vgaattr[] = {0x00, 0x00, 0x00, 0x00, 0x00,
@@ -464,7 +464,7 @@ static FxU16 modeData[21] =
ISET8PHYS(0x0d4, _srcindex); \
modeData[_dstindex] = IGET8PHYS(0x0d5);
void
static void
buildVideoModeData(hwcBoardInfo *bInfo)
{
/* Snarf all VGA data we need from the master */
@@ -513,7 +513,7 @@ buildVideoModeData(hwcBoardInfo *bInfo)
}
}
void
static void
setVideoModeSlave(
FxU32 regBase) // regBase of the slave
{
@@ -866,7 +866,7 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
} else if(!sliEnable && aaEnable) {
/* SLI disabled, AA enabled */
CFG_WRITE(chipNum, cfgSliLfbCtrl, 0);
} else {
} else {
/* SLI enabled, AA enabled, 4 sample AA enabled */
sliRenderMask = ((numChips >> 1) - 1) << sliBandHeightLog2;
sliCompareMask = (chipNum >> 1) << sliBandHeightLog2;
@@ -1180,9 +1180,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0x00);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else if(chipNum == 1 || chipNum == 3) {
/* Second and fourth chips */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1197,9 +1197,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0xff);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else {
/* Third chip */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1229,9 +1229,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0x00);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else if(chipNum == 1 || chipNum == 3) {
/* Second and fourth chips */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1247,9 +1247,9 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
0xff);
if(vid2xMode) {
CFG_VIDEOCTRL2(0x00, 0xff);
} else {
} else {
CFG_VIDEOCTRL2(0x00, 0x00);
}
}
} else {
/* Third chip */
CFG_VIDEOCTRL0(SST_CFG_ENHANCED_VIDEO_EN |
@@ -1540,4 +1540,3 @@ void hwcSetSLIAAMode(hwcBoardInfo *bInfo,
}
}
}