From d50c3ff48fdaa3cf12e36acb85cd1acd1b4729dd Mon Sep 17 00:00:00 2001 From: chacha <15073640+cclecle@users.noreply.github.com> Date: Mon, 23 Feb 2026 11:32:57 +0100 Subject: [PATCH] first commit --- .gitignore | 4 + Draw.c | 33 ++ Draw.h | 6 + FaultSources.c | 327 +++++++++++++++ FaultSources.h | 1027 ++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 21 + Readme.md | 0 Test_Address.c | 574 ++++++++++++++++++++++++++ Test_Address.h | 11 + Test_Data.c | 661 +++++++++++++++++++++++++++++ Test_Data.h | 12 + Test_Data_Huge.c | 248 +++++++++++ Test_Data_Huge.h | 11 + Utils.c | 102 +++++ Utils.h | 13 + main.c | 157 +++++++ 16 files changed, 3207 insertions(+) create mode 100644 .gitignore create mode 100644 Draw.c create mode 100644 Draw.h create mode 100644 FaultSources.c create mode 100644 FaultSources.h create mode 100644 Makefile create mode 100644 Readme.md create mode 100644 Test_Address.c create mode 100644 Test_Address.h create mode 100644 Test_Data.c create mode 100644 Test_Data.h create mode 100644 Test_Data_Huge.c create mode 100644 Test_Data_Huge.h create mode 100644 Utils.c create mode 100644 Utils.h create mode 100644 main.c diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..379a21c --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +*~ +*.o +*.log +V2MemTest \ No newline at end of file diff --git a/Draw.c b/Draw.c new file mode 100644 index 0000000..10bded2 --- /dev/null +++ b/Draw.c @@ -0,0 +1,33 @@ +#include +#include + +#include "Draw.h" + +#define XY_ONE (1<vA.x,x); + ISET(sst->vA.y,y); + ISET(sst->vB.x,x+XY_ONE*tSize); + ISET(sst->vB.y,y); + ISET(sst->vC.x,x); + ISET(sst->vC.y,y+XY_ONE*tSize); + ISET(sst->s,0); + ISET(sst->t,0); + ISET(sst->w,0); + ISET(sst->dsdx,1<dtdx,0); + ISET(sst->dwdx,0); + ISET(sst->dsdy,0); + ISET(sst->dtdy,1<dwdy,0); + ISET(sst->triangleCMD,0); + ISET(sst->vB.x, (x<vB.y, ((y+tSize)<triangleCMD, 0xFFFFFFFF); +} diff --git a/Draw.h b/Draw.h new file mode 100644 index 0000000..986e273 --- /dev/null +++ b/Draw.h @@ -0,0 +1,6 @@ +#ifndef _DEF_DRAW_H_ +#define _DEF_DRAW_H_ + +void drawTriangle( const SstRegs *sst, const int x, const int y, const int tSize); + +#endif //_DEF_DRAW_H_ diff --git a/FaultSources.c b/FaultSources.c new file mode 100644 index 0000000..43375eb --- /dev/null +++ b/FaultSources.c @@ -0,0 +1,327 @@ +#include +#include + +#include "FaultSources.h" +#include "Utils.h" + +def_sFaultSourceScoreRec ar_dFaultScores[NB_FAULT_SOURCE] = +{ + { + .eThisFaultSource = VOODOO_BOARD, + .szName = "VOODOO_BOARD", + .szLoc = "Main Board", + .eParrentFaultSource = _INVALID_FAULT_SOURCE_, + .dScore = 0.0 + }, + FAULT_SOURCES(GEN_FAULT_SOURCES_ARRAY) +}; + +def_sFaultSourceScoreRec ar_dFaultScores_sorted[NB_FAULT_SOURCE]; + +void +FaultSource_Reset() +{ + for(def_eFaultSource idx=0;idx=0; + eFaultSourceCurrentComp--) + { + if( ar_dFaultScores_sorted[eFaultSourceCurrentComp].dScore + < ar_dFaultScores_sorted[eFaultSourceCurrentComp+1].dScore) + { + FaultSource_Sort_Swap(eFaultSourceCurrentComp,eFaultSourceCurrentComp+1); + bSwapped=1; + break; + } + } + } + + // updating refs + for(long eFaultSourceIdx=0; + eFaultSourceIdx%s",ar_dFaultScores_sorted[eFaultSource].szLoc,loc); + strcpy(loc,buff); + eFaultSource = ar_dFaultScores_sorted[eFaultSource].eParrentFaultSource; + } +} + +void +FaultSource_Display() +{ + double dScoreSum = 0; + + for(def_eFaultSource eFaultSourceCurrent=0; + eFaultSourceCurrent < NB_FAULT_SOURCE && ar_dFaultScores_sorted[eFaultSourceCurrent].dScore > 0; + eFaultSourceCurrent++ ) + dScoreSum+=ar_dFaultScores_sorted[eFaultSourceCurrent].dScore; + + printf("------------------------------------------------\n"); + printf("\nDefects list:\n\n"); + printf("Score\tElement [Loc]\n"); + printf("------------------------------------------------\n"); + for(def_eFaultSource eFaultSourceCurrent=0; + eFaultSourceCurrent < NB_FAULT_SOURCE + && (ar_dFaultScores_sorted[eFaultSourceCurrent].dScore > 0); + eFaultSourceCurrent++ ) + { + static char buff[1024]; + FaultSource_GetLoc(eFaultSourceCurrent,buff); + printf("%02.3f\t%s [%s]\n", + 100*ar_dFaultScores_sorted[eFaultSourceCurrent].dScore/dScoreSum, + ar_dFaultScores_sorted[eFaultSourceCurrent].szName, + buff); + } +} + + +void +WordBitFaultSet( const unsigned long ErrorMark, + const double dScore, + const def_eFaultSource eFaultSourceL, + const def_eFaultSource eFaultSourceH) +{ + /* loop unrolling optimization + for(unsigned long bitPos = 0; bitPos <= 31 ; bitPos++) + { + if(ErrorMark & (1< 16) ) + { + if(ErrorMark & 0x000000FF) + FaultSource_AddScore(eFaultSourceCASL,dScore/2); + if(ErrorMark & 0x0000FF00) + FaultSource_AddScore(eFaultSourceCASH,dScore/2); + if(ErrorMark & 0x00FF0000) + FaultSource_AddScore(eFaultSourceCASL,dScore/2); + if(ErrorMark & 0xFF000000) + FaultSource_AddScore(eFaultSourceCASH,dScore/2); + + FaultSource_AddScore(eFaultSourceRAS,dScore/4); + FaultSource_AddScore(eFaultSourceWE,dScore/4); + } +} + diff --git a/FaultSources.h b/FaultSources.h new file mode 100644 index 0000000..6d28e84 --- /dev/null +++ b/FaultSources.h @@ -0,0 +1,1027 @@ + +#ifndef _DEF_FAULTSOURCES_H_ +#define _DEF_FAULTSOURCES_H_ + +#define FAULT_SOURCES(ACTION) \ + ACTION(U3_FBI,"U3/FBI (front middle big Chip)",VOODOO_BOARD)\ + ACTION(U9_TMU0,"U9/TMU0 (front right big Chip)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U9_TMU0_TEXDATA_0_0,"pin 52",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_1,"pin 53",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_2,"pin 54",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_3,"pin 55",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_4,"pin 56",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_5,"pin 57",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_6,"pin 59",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_7,"pin 60",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_8,"pin 61",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_9,"pin 62",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_10,"pin 64",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_11,"pin 65",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_12,"pin 66",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_13,"pin 67",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_14,"pin 69",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_0_15,"pin 70",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_0,"pin 90",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_1,"pin 91",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_2,"pin 92",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_3,"pin 93",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_4,"pin 94",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_5,"pin 95",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_6,"pin 98",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_7,"pin 98",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_8,"pin 100",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_9,"pin 101",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_10,"pin 103",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_11,"pin 104",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_12,"pin 105",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_13,"pin 106",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_14,"pin 107",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_1_15,"pin 108",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_0,"pin 71",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_1,"pin 72",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_2,"pin 74",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_3,"pin 75",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_4,"pin 76",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_5,"pin 77",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_6,"pin 79",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_7,"pin 80",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_8,"pin 81",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_9,"pin 82",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_10,"pin 84",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_11,"pin 85",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_12,"pin 86",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_13,"pin 87",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_14,"pin 88",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_2_15,"pin 89",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_0,"pin 110",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_1,"pin 111",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_2,"pin 112",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_3,"pin 113",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_4,"pin 114",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_5,"pin 115",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_6,"pin 117",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_7,"pin 118",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_8,"pin 119",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_9,"pin 120",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_10,"pin 122",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_11,"pin 123",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_12,"pin 124",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_13,"pin 125",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_14,"pin 126",U9_TMU0)\ + ACTION(U9_TMU0_TEXDATA_3_15,"pin 127",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_0,"pin 188",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_1,"pin 189",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_2,"pin 190",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_3,"pin 191",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_4,"pin 192",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_5,"pin 193",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_6,"pin 194",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_7,"pin 195",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_8,"pin 199",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_9,"pin 200",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_10,"pin 201",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_11,"pin 202",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_12,"pin 204",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_13,"pin 205",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_14,"pin 206",U9_TMU0)\ + ACTION(U9_TMU0_TT_DATA_15,"pin 207",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_0,"pin 6",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_1,"pin 7",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_2,"pin 8",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_3,"pin 9",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_4,"pin 10",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_5,"pin 11",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_6,"pin 12",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_7,"pin 16",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_8,"pin 17",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_9,"pin 18",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_10,"pin 19",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_11,"pin 20",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_12,"pin 22",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_13,"pin 23",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_14,"pin 24",U9_TMU0)\ + ACTION(U9_TMU0_FT_DATA_15,"pin 25",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_0,"pin 30",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_1,"pin 32",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_2,"pin 33",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_3,"pin 34",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_4,"pin 35",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_5,"pin 36",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_6,"pin 37",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_7,"pin 38",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_8,"pin 42",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_9,"pin 44",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_10,"pin 45",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_11,"pin 46",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_12,"pin 47",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_13,"pin 48",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_14,"pin 49",U9_TMU0)\ + ACTION(U9_TMU0_TF_DATA_15,"pin 80",U9_TMU0)\ + ACTION(U9_TMU0_TEX_RAS0,"pin 129",U9_TMU0)\ + ACTION(U9_TMU0_TEX_RAS1,"pin 130",U9_TMU0)\ + ACTION(U9_TMU0_TEX_CAS0,"pin 131",U9_TMU0)\ + ACTION(U9_TMU0_TEX_CAS1,"pin 132",U9_TMU0)\ + ACTION(U9_TMU0_TEX_CAS2,"pin 134",U9_TMU0)\ + ACTION(U9_TMU0_TEX_CAS3,"pin 135",U9_TMU0)\ + ACTION(U9_TMU0_TEX_WE,"pin 136",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_0,"pin 138",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_1,"pin 139",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_2,"pin 141",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_3,"pin 142",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_4,"pin 144",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_5,"pin 145",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_6,"pin 146",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_7,"pin 147",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_0_8,"pin 149",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_0,"pin 161",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_1,"pin 162",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_2,"pin 164",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_3,"pin 165",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_4,"pin 166",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_5,"pin 167",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_6,"pin 168",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_7,"pin 169",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_1_8,"pin 171",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_0,"pin 150",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_1,"pin 151",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_2,"pin 152",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_3,"pin 154",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_4,"pin 155",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_5,"pin 156",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_6,"pin 157",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_7,"pin 158",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_2_8,"pin 160",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_0,"pin 172",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_1,"pin 174",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_2,"pin 175",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_3,"pin 176",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_4,"pin 177",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_5,"pin 178",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_6,"pin 179",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_7,"pin 180",U9_TMU0)\ + ACTION(U9_TMU0_TEX_ADDR_3_8,"pin 182",U9_TMU0)\ + ACTION(U8_TMU1,"U8/TMU1 (front left big Chip)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U8_TMU1_TEXDATA_0_0,"pin 52",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_1,"pin 53",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_2,"pin 54",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_3,"pin 55",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_4,"pin 56",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_5,"pin 57",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_6,"pin 59",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_7,"pin 60",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_8,"pin 61",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_9,"pin 62",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_10,"pin 64",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_11,"pin 65",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_12,"pin 66",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_13,"pin 67",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_14,"pin 69",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_0_15,"pin 70",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_0,"pin 90",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_1,"pin 91",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_2,"pin 92",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_3,"pin 93",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_4,"pin 94",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_5,"pin 95",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_6,"pin 98",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_7,"pin 98",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_8,"pin 100",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_9,"pin 101",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_10,"pin 103",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_11,"pin 104",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_12,"pin 105",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_13,"pin 106",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_14,"pin 107",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_1_15,"pin 108",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_0,"pin 71",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_1,"pin 72",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_2,"pin 74",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_3,"pin 75",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_4,"pin 76",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_5,"pin 77",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_6,"pin 79",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_7,"pin 80",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_8,"pin 81",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_9,"pin 82",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_10,"pin 84",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_11,"pin 85",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_12,"pin 86",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_13,"pin 87",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_14,"pin 88",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_2_15,"pin 89",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_0,"pin 110",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_1,"pin 111",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_2,"pin 112",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_3,"pin 113",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_4,"pin 114",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_5,"pin 115",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_6,"pin 117",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_7,"pin 118",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_8,"pin 119",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_9,"pin 120",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_10,"pin 122",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_11,"pin 123",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_12,"pin 124",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_13,"pin 125",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_14,"pin 126",U8_TMU1)\ + ACTION(U8_TMU1_TEXDATA_3_15,"pin 127",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_0,"pin 30",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_1,"pin 32",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_2,"pin 33",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_3,"pin 34",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_4,"pin 35",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_5,"pin 36",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_6,"pin 37",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_7,"pin 38",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_8,"pin 42",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_9,"pin 44",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_10,"pin 45",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_11,"pin 46",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_12,"pin 47",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_13,"pin 48",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_14,"pin 49",U8_TMU1)\ + ACTION(U8_TMU1_TF_DATA_15,"pin 80",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_0,"pin 6",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_1,"pin 7",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_2,"pin 8",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_3,"pin 9",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_4,"pin 10",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_5,"pin 11",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_6,"pin 12",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_7,"pin 16",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_8,"pin 17",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_9,"pin 18",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_10,"pin 19",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_11,"pin 20",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_12,"pin 22",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_13,"pin 23",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_14,"pin 24",U8_TMU1)\ + ACTION(U8_TMU1_FT_DATA_15,"pin 25",U8_TMU1)\ + ACTION(U8_TMU1_TEX_RAS0,"pin 129",U8_TMU1)\ + ACTION(U8_TMU1_TEX_RAS1,"pin 130",U8_TMU1)\ + ACTION(U8_TMU1_TEX_CAS0,"pin 131",U8_TMU1)\ + ACTION(U8_TMU1_TEX_CAS1,"pin 132",U8_TMU1)\ + ACTION(U8_TMU1_TEX_CAS2,"pin 134",U8_TMU1)\ + ACTION(U8_TMU1_TEX_CAS3,"pin 135",U8_TMU1)\ + ACTION(U8_TMU1_TEX_WE,"pin 136",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_0,"pin 138",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_1,"pin 139",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_2,"pin 141",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_3,"pin 142",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_4,"pin 144",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_5,"pin 145",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_6,"pin 146",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_7,"pin 147",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_0_8,"pin 149",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_0,"pin 161",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_1,"pin 162",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_2,"pin 164",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_3,"pin 165",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_4,"pin 166",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_5,"pin 167",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_6,"pin 168",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_7,"pin 169",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_1_8,"pin 171",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_0,"pin 150",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_1,"pin 151",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_2,"pin 152",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_3,"pin 154",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_4,"pin 155",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_5,"pin 156",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_6,"pin 157",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_7,"pin 158",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_2_8,"pin 160",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_0,"pin 172",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_1,"pin 174",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_2,"pin 175",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_3,"pin 176",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_4,"pin 177",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_5,"pin 178",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_6,"pin 179",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_7,"pin 180",U8_TMU1)\ + ACTION(U8_TMU1_TEX_ADDR_3_8,"pin 182",U8_TMU1)\ + ACTION(U11,"U11/RAM (front left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U11_DQ0,"pin 2",U11)\ + ACTION(U11_DQ1,"pin 3",U11)\ + ACTION(U11_DQ2,"pin 4",U11)\ + ACTION(U11_DQ3,"pin 5",U11)\ + ACTION(U11_DQ4,"pin 7",U11)\ + ACTION(U11_DQ5,"pin 8",U11)\ + ACTION(U11_DQ6,"pin 9",U11)\ + ACTION(U11_DQ7,"pin 10",U11)\ + ACTION(U11_DQ8,"pin 31",U11)\ + ACTION(U11_DQ9,"pin 32",U11)\ + ACTION(U11_DQ10,"pin 33",U11)\ + ACTION(U11_DQ11,"pin 34",U11)\ + ACTION(U11_DQ12,"pin 36",U11)\ + ACTION(U11_DQ13,"pin 37",U11)\ + ACTION(U11_DQ14,"pin 38",U11)\ + ACTION(U11_DQ15,"pin 39",U11)\ + ACTION(U11_A0,"pin 16",U11)\ + ACTION(U11_A1,"pin 17",U11)\ + ACTION(U11_A2,"pin 18",U11)\ + ACTION(U11_A3,"pin 19",U11)\ + ACTION(U11_A4,"pin 22",U11)\ + ACTION(U11_A5,"pin 23",U11)\ + ACTION(U11_A6,"pin 24",U11)\ + ACTION(U11_A7,"pin 25",U11)\ + ACTION(U11_A8,"pin 26",U11)\ + ACTION(U11_CASH,"pin 28",U11)\ + ACTION(U11_CASL,"pin 29",U11)\ + ACTION(U11_RAS,"pin 14",U11)\ + ACTION(U11_WE,"pin 13",U11)\ + ACTION(U12,"U12/RAM (front right)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U12_DQ0,"pin 2",U12)\ + ACTION(U12_DQ1,"pin 3",U12)\ + ACTION(U12_DQ2,"pin 4",U12)\ + ACTION(U12_DQ3,"pin 5",U12)\ + ACTION(U12_DQ4,"pin 7",U12)\ + ACTION(U12_DQ5,"pin 8",U12)\ + ACTION(U12_DQ6,"pin 9",U12)\ + ACTION(U12_DQ7,"pin 10",U12)\ + ACTION(U12_DQ8,"pin 31",U12)\ + ACTION(U12_DQ9,"pin 32",U12)\ + ACTION(U12_DQ10,"pin 33",U12)\ + ACTION(U12_DQ11,"pin 34",U12)\ + ACTION(U12_DQ12,"pin 36",U12)\ + ACTION(U12_DQ13,"pin 37",U12)\ + ACTION(U12_DQ14,"pin 38",U12)\ + ACTION(U12_DQ15,"pin 39",U12)\ + ACTION(U12_A0,"pin 16",U12)\ + ACTION(U12_A1,"pin 17",U12)\ + ACTION(U12_A2,"pin 18",U12)\ + ACTION(U12_A3,"pin 19",U12)\ + ACTION(U12_A4,"pin 22",U12)\ + ACTION(U12_A5,"pin 23",U12)\ + ACTION(U12_A6,"pin 24",U12)\ + ACTION(U12_A7,"pin 25",U12)\ + ACTION(U12_A8,"pin 26",U12)\ + ACTION(U12_CASH,"pin 28",U12)\ + ACTION(U12_CASL,"pin 29",U12)\ + ACTION(U12_RAS,"pin 14",U12)\ + ACTION(U12_WE,"pin 13",U12)\ + ACTION(U13,"U13/RAM (front left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U13_DQ0,"pin 2",U13)\ + ACTION(U13_DQ1,"pin 3",U13)\ + ACTION(U13_DQ2,"pin 4",U13)\ + ACTION(U13_DQ3,"pin 5",U13)\ + ACTION(U13_DQ4,"pin 7",U13)\ + ACTION(U13_DQ5,"pin 8",U13)\ + ACTION(U13_DQ6,"pin 9",U13)\ + ACTION(U13_DQ7,"pin 10",U13)\ + ACTION(U13_DQ8,"pin 31",U13)\ + ACTION(U13_DQ9,"pin 32",U13)\ + ACTION(U13_DQ10,"pin 33",U13)\ + ACTION(U13_DQ11,"pin 34",U13)\ + ACTION(U13_DQ12,"pin 36",U13)\ + ACTION(U13_DQ13,"pin 37",U13)\ + ACTION(U13_DQ14,"pin 38",U13)\ + ACTION(U13_DQ15,"pin 39",U13)\ + ACTION(U13_A0,"pin 16",U13)\ + ACTION(U13_A1,"pin 17",U13)\ + ACTION(U13_A2,"pin 18",U13)\ + ACTION(U13_A3,"pin 19",U13)\ + ACTION(U13_A4,"pin 22",U13)\ + ACTION(U13_A5,"pin 23",U13)\ + ACTION(U13_A6,"pin 24",U13)\ + ACTION(U13_A7,"pin 25",U13)\ + ACTION(U13_A8,"pin 26",U13)\ + ACTION(U13_CASH,"pin 28",U13)\ + ACTION(U13_CASL,"pin 29",U13)\ + ACTION(U13_RAS,"pin 14",U13)\ + ACTION(U13_WE,"pin 13",U13)\ + ACTION(U14,"U14/RAM (front right)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U14_DQ0,"pin 2",U14)\ + ACTION(U14_DQ1,"pin 3",U14)\ + ACTION(U14_DQ2,"pin 4",U14)\ + ACTION(U14_DQ3,"pin 5",U14)\ + ACTION(U14_DQ4,"pin 7",U14)\ + ACTION(U14_DQ5,"pin 8",U14)\ + ACTION(U14_DQ6,"pin 9",U14)\ + ACTION(U14_DQ7,"pin 10",U14)\ + ACTION(U14_DQ8,"pin 31",U14)\ + ACTION(U14_DQ9,"pin 32",U14)\ + ACTION(U14_DQ10,"pin 33",U14)\ + ACTION(U14_DQ11,"pin 34",U14)\ + ACTION(U14_DQ12,"pin 36",U14)\ + ACTION(U14_DQ13,"pin 37",U14)\ + ACTION(U14_DQ14,"pin 38",U14)\ + ACTION(U14_DQ15,"pin 39",U14)\ + ACTION(U14_A0,"pin 16",U14)\ + ACTION(U14_A1,"pin 17",U14)\ + ACTION(U14_A2,"pin 18",U14)\ + ACTION(U14_A3,"pin 19",U14)\ + ACTION(U14_A4,"pin 22",U14)\ + ACTION(U14_A5,"pin 23",U14)\ + ACTION(U14_A6,"pin 24",U14)\ + ACTION(U14_A7,"pin 25",U14)\ + ACTION(U14_A8,"pin 26",U14)\ + ACTION(U14_CASH,"pin 28",U14)\ + ACTION(U14_CASL,"pin 29",U14)\ + ACTION(U14_RAS,"pin 14",U14)\ + ACTION(U14_WE,"pin 13",U14)\ + ACTION(U15,"U15/RAM (front left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U15_DQ0,"pin 2",U15)\ + ACTION(U15_DQ1,"pin 3",U15)\ + ACTION(U15_DQ2,"pin 4",U15)\ + ACTION(U15_DQ3,"pin 5",U15)\ + ACTION(U15_DQ4,"pin 7",U15)\ + ACTION(U15_DQ5,"pin 8",U15)\ + ACTION(U15_DQ6,"pin 9",U15)\ + ACTION(U15_DQ7,"pin 10",U15)\ + ACTION(U15_DQ8,"pin 31",U15)\ + ACTION(U15_DQ9,"pin 32",U15)\ + ACTION(U15_DQ10,"pin 33",U15)\ + ACTION(U15_DQ11,"pin 34",U15)\ + ACTION(U15_DQ12,"pin 36",U15)\ + ACTION(U15_DQ13,"pin 37",U15)\ + ACTION(U15_DQ14,"pin 38",U15)\ + ACTION(U15_DQ15,"pin 39",U15)\ + ACTION(U15_A0,"pin 16",U15)\ + ACTION(U15_A1,"pin 17",U15)\ + ACTION(U15_A2,"pin 18",U15)\ + ACTION(U15_A3,"pin 19",U15)\ + ACTION(U15_A4,"pin 22",U15)\ + ACTION(U15_A5,"pin 23",U15)\ + ACTION(U15_A6,"pin 24",U15)\ + ACTION(U15_A7,"pin 25",U15)\ + ACTION(U15_A8,"pin 26",U15)\ + ACTION(U15_CASH,"pin 28",U15)\ + ACTION(U15_CASL,"pin 29",U15)\ + ACTION(U15_RAS,"pin 14",U15)\ + ACTION(U15_WE,"pin 13",U15)\ + ACTION(U16,"U16/RAM (front left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U16_DQ0,"pin 2",U16)\ + ACTION(U16_DQ1,"pin 3",U16)\ + ACTION(U16_DQ2,"pin 4",U16)\ + ACTION(U16_DQ3,"pin 5",U16)\ + ACTION(U16_DQ4,"pin 7",U16)\ + ACTION(U16_DQ5,"pin 8",U16)\ + ACTION(U16_DQ6,"pin 9",U16)\ + ACTION(U16_DQ7,"pin 10",U16)\ + ACTION(U16_DQ8,"pin 31",U16)\ + ACTION(U16_DQ9,"pin 32",U16)\ + ACTION(U16_DQ10,"pin 33",U16)\ + ACTION(U16_DQ11,"pin 34",U16)\ + ACTION(U16_DQ12,"pin 36",U16)\ + ACTION(U16_DQ13,"pin 37",U16)\ + ACTION(U16_DQ14,"pin 38",U16)\ + ACTION(U16_DQ15,"pin 39",U16)\ + ACTION(U16_A0,"pin 16",U16)\ + ACTION(U16_A1,"pin 17",U16)\ + ACTION(U16_A2,"pin 18",U16)\ + ACTION(U16_A3,"pin 19",U16)\ + ACTION(U16_A4,"pin 22",U16)\ + ACTION(U16_A5,"pin 23",U16)\ + ACTION(U16_A6,"pin 24",U16)\ + ACTION(U16_A7,"pin 25",U16)\ + ACTION(U16_A8,"pin 26",U16)\ + ACTION(U16_CASH,"pin 28",U16)\ + ACTION(U16_CASL,"pin 29",U16)\ + ACTION(U16_RAS,"pin 14",U16)\ + ACTION(U16_WE,"pin 13",U16)\ + ACTION(U17,"U17/RAM (front right)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U17_DQ0,"pin 2",U17)\ + ACTION(U17_DQ1,"pin 3",U17)\ + ACTION(U17_DQ2,"pin 4",U17)\ + ACTION(U17_DQ3,"pin 5",U17)\ + ACTION(U17_DQ4,"pin 7",U17)\ + ACTION(U17_DQ5,"pin 8",U17)\ + ACTION(U17_DQ6,"pin 9",U17)\ + ACTION(U17_DQ7,"pin 10",U17)\ + ACTION(U17_DQ8,"pin 31",U17)\ + ACTION(U17_DQ9,"pin 32",U17)\ + ACTION(U17_DQ10,"pin 33",U17)\ + ACTION(U17_DQ11,"pin 34",U17)\ + ACTION(U17_DQ12,"pin 36",U17)\ + ACTION(U17_DQ13,"pin 37",U17)\ + ACTION(U17_DQ14,"pin 38",U17)\ + ACTION(U17_DQ15,"pin 39",U17)\ + ACTION(U17_A0,"pin 16",U17)\ + ACTION(U17_A1,"pin 17",U17)\ + ACTION(U17_A2,"pin 18",U17)\ + ACTION(U17_A3,"pin 19",U17)\ + ACTION(U17_A4,"pin 22",U17)\ + ACTION(U17_A5,"pin 23",U17)\ + ACTION(U17_A6,"pin 24",U17)\ + ACTION(U17_A7,"pin 25",U17)\ + ACTION(U17_A8,"pin 26",U17)\ + ACTION(U17_CASH,"pin 28",U17)\ + ACTION(U17_CASL,"pin 29",U17)\ + ACTION(U17_RAS,"pin 14",U17)\ + ACTION(U17_WE,"pin 13",U17)\ + ACTION(U18,"U18/RAM (front right)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U18_DQ0,"pin 2",U18)\ + ACTION(U18_DQ1,"pin 3",U18)\ + ACTION(U18_DQ2,"pin 4",U18)\ + ACTION(U18_DQ3,"pin 5",U18)\ + ACTION(U18_DQ4,"pin 7",U18)\ + ACTION(U18_DQ5,"pin 8",U18)\ + ACTION(U18_DQ6,"pin 9",U18)\ + ACTION(U18_DQ7,"pin 10",U18)\ + ACTION(U18_DQ8,"pin 31",U18)\ + ACTION(U18_DQ9,"pin 32",U18)\ + ACTION(U18_DQ10,"pin 33",U18)\ + ACTION(U18_DQ11,"pin 34",U18)\ + ACTION(U18_DQ12,"pin 36",U18)\ + ACTION(U18_DQ13,"pin 37",U18)\ + ACTION(U18_DQ14,"pin 38",U18)\ + ACTION(U18_DQ15,"pin 39",U18)\ + ACTION(U18_A0,"pin 16",U18)\ + ACTION(U18_A1,"pin 17",U18)\ + ACTION(U18_A2,"pin 18",U18)\ + ACTION(U18_A3,"pin 19",U18)\ + ACTION(U18_A4,"pin 22",U18)\ + ACTION(U18_A5,"pin 23",U18)\ + ACTION(U18_A6,"pin 24",U18)\ + ACTION(U18_A7,"pin 25",U18)\ + ACTION(U18_A8,"pin 26",U18)\ + ACTION(U18_CASH,"pin 28",U18)\ + ACTION(U18_CASL,"pin 29",U18)\ + ACTION(U18_RAS,"pin 14",U18)\ + ACTION(U18_WE,"pin 13",U18)\ + ACTION(U23,"U23/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U23_DQ0,"pin 2",U23)\ + ACTION(U23_DQ1,"pin 3",U23)\ + ACTION(U23_DQ2,"pin 4",U23)\ + ACTION(U23_DQ3,"pin 5",U23)\ + ACTION(U23_DQ4,"pin 7",U23)\ + ACTION(U23_DQ5,"pin 8",U23)\ + ACTION(U23_DQ6,"pin 9",U23)\ + ACTION(U23_DQ7,"pin 10",U23)\ + ACTION(U23_DQ8,"pin 31",U23)\ + ACTION(U23_DQ9,"pin 32",U23)\ + ACTION(U23_DQ10,"pin 33",U23)\ + ACTION(U23_DQ11,"pin 34",U23)\ + ACTION(U23_DQ12,"pin 36",U23)\ + ACTION(U23_DQ13,"pin 37",U23)\ + ACTION(U23_DQ14,"pin 38",U23)\ + ACTION(U23_DQ15,"pin 39",U23)\ + ACTION(U23_A0,"pin 16",U23)\ + ACTION(U23_A1,"pin 17",U23)\ + ACTION(U23_A2,"pin 18",U23)\ + ACTION(U23_A3,"pin 19",U23)\ + ACTION(U23_A4,"pin 22",U23)\ + ACTION(U23_A5,"pin 23",U23)\ + ACTION(U23_A6,"pin 24",U23)\ + ACTION(U23_A7,"pin 25",U23)\ + ACTION(U23_A8,"pin 26",U23)\ + ACTION(U23_CASH,"pin 28",U23)\ + ACTION(U23_CASL,"pin 29",U23)\ + ACTION(U23_RAS,"pin 14",U23)\ + ACTION(U23_WE,"pin 13",U23)\ + ACTION(U24,"U24/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U24_DQ0,"pin 2",U24)\ + ACTION(U24_DQ1,"pin 3",U24)\ + ACTION(U24_DQ2,"pin 4",U24)\ + ACTION(U24_DQ3,"pin 5",U24)\ + ACTION(U24_DQ4,"pin 7",U24)\ + ACTION(U24_DQ5,"pin 8",U24)\ + ACTION(U24_DQ6,"pin 9",U24)\ + ACTION(U24_DQ7,"pin 10",U24)\ + ACTION(U24_DQ8,"pin 31",U24)\ + ACTION(U24_DQ9,"pin 32",U24)\ + ACTION(U24_DQ10,"pin 33",U24)\ + ACTION(U24_DQ11,"pin 34",U24)\ + ACTION(U24_DQ12,"pin 36",U24)\ + ACTION(U24_DQ13,"pin 37",U24)\ + ACTION(U24_DQ14,"pin 38",U24)\ + ACTION(U24_DQ15,"pin 39",U24)\ + ACTION(U24_A0,"pin 16",U24)\ + ACTION(U24_A1,"pin 17",U24)\ + ACTION(U24_A2,"pin 18",U24)\ + ACTION(U24_A3,"pin 19",U24)\ + ACTION(U24_A4,"pin 22",U24)\ + ACTION(U24_A5,"pin 23",U24)\ + ACTION(U24_A6,"pin 24",U24)\ + ACTION(U24_A7,"pin 25",U24)\ + ACTION(U24_A8,"pin 26",U24)\ + ACTION(U24_CASH,"pin 28",U24)\ + ACTION(U24_CASL,"pin 29",U24)\ + ACTION(U24_RAS,"pin 14",U24)\ + ACTION(U24_WE,"pin 13",U24)\ + ACTION(U25,"U25/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U25_DQ0,"pin 2",U25)\ + ACTION(U25_DQ1,"pin 3",U25)\ + ACTION(U25_DQ2,"pin 4",U25)\ + ACTION(U25_DQ3,"pin 5",U25)\ + ACTION(U25_DQ4,"pin 7",U25)\ + ACTION(U25_DQ5,"pin 8",U25)\ + ACTION(U25_DQ6,"pin 9",U25)\ + ACTION(U25_DQ7,"pin 10",U25)\ + ACTION(U25_DQ8,"pin 31",U25)\ + ACTION(U25_DQ9,"pin 32",U25)\ + ACTION(U25_DQ10,"pin 33",U25)\ + ACTION(U25_DQ11,"pin 34",U25)\ + ACTION(U25_DQ12,"pin 36",U25)\ + ACTION(U25_DQ13,"pin 37",U25)\ + ACTION(U25_DQ14,"pin 38",U25)\ + ACTION(U25_DQ15,"pin 39",U25)\ + ACTION(U25_A0,"pin 16",U25)\ + ACTION(U25_A1,"pin 17",U25)\ + ACTION(U25_A2,"pin 18",U25)\ + ACTION(U25_A3,"pin 19",U25)\ + ACTION(U25_A4,"pin 22",U25)\ + ACTION(U25_A5,"pin 23",U25)\ + ACTION(U25_A6,"pin 24",U25)\ + ACTION(U25_A7,"pin 25",U25)\ + ACTION(U25_A8,"pin 26",U25)\ + ACTION(U25_CASH,"pin 28",U25)\ + ACTION(U25_CASL,"pin 29",U25)\ + ACTION(U25_RAS,"pin 14",U25)\ + ACTION(U25_WE,"pin 13",U25)\ + ACTION(U26,"U26/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U26_DQ0,"pin 2",U26)\ + ACTION(U26_DQ1,"pin 3",U26)\ + ACTION(U26_DQ2,"pin 4",U26)\ + ACTION(U26_DQ3,"pin 5",U26)\ + ACTION(U26_DQ4,"pin 7",U26)\ + ACTION(U26_DQ5,"pin 8",U26)\ + ACTION(U26_DQ6,"pin 9",U26)\ + ACTION(U26_DQ7,"pin 10",U26)\ + ACTION(U26_DQ8,"pin 31",U26)\ + ACTION(U26_DQ9,"pin 32",U26)\ + ACTION(U26_DQ10,"pin 33",U26)\ + ACTION(U26_DQ11,"pin 34",U26)\ + ACTION(U26_DQ12,"pin 36",U26)\ + ACTION(U26_DQ13,"pin 37",U26)\ + ACTION(U26_DQ14,"pin 38",U26)\ + ACTION(U26_DQ15,"pin 39",U26)\ + ACTION(U26_A0,"pin 16",U26)\ + ACTION(U26_A1,"pin 17",U26)\ + ACTION(U26_A2,"pin 18",U26)\ + ACTION(U26_A3,"pin 19",U26)\ + ACTION(U26_A4,"pin 22",U26)\ + ACTION(U26_A5,"pin 23",U26)\ + ACTION(U26_A6,"pin 24",U26)\ + ACTION(U26_A7,"pin 25",U26)\ + ACTION(U26_A8,"pin 26",U26)\ + ACTION(U26_CASH,"pin 28",U26)\ + ACTION(U26_CASL,"pin 29",U26)\ + ACTION(U26_RAS,"pin 14",U26)\ + ACTION(U26_WE,"pin 13",U26)\ + ACTION(U27,"U27/RAM (back right)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U27_DQ0,"pin 2",U27)\ + ACTION(U27_DQ1,"pin 3",U27)\ + ACTION(U27_DQ2,"pin 4",U27)\ + ACTION(U27_DQ3,"pin 5",U27)\ + ACTION(U27_DQ4,"pin 7",U27)\ + ACTION(U27_DQ5,"pin 8",U27)\ + ACTION(U27_DQ6,"pin 9",U27)\ + ACTION(U27_DQ7,"pin 10",U27)\ + ACTION(U27_DQ8,"pin 31",U27)\ + ACTION(U27_DQ9,"pin 32",U27)\ + ACTION(U27_DQ10,"pin 33",U27)\ + ACTION(U27_DQ11,"pin 34",U27)\ + ACTION(U27_DQ12,"pin 36",U27)\ + ACTION(U27_DQ13,"pin 37",U27)\ + ACTION(U27_DQ14,"pin 38",U27)\ + ACTION(U27_DQ15,"pin 39",U27)\ + ACTION(U27_A0,"pin 16",U27)\ + ACTION(U27_A1,"pin 17",U27)\ + ACTION(U27_A2,"pin 18",U27)\ + ACTION(U27_A3,"pin 19",U27)\ + ACTION(U27_A4,"pin 22",U27)\ + ACTION(U27_A5,"pin 23",U27)\ + ACTION(U27_A6,"pin 24",U27)\ + ACTION(U27_A7,"pin 25",U27)\ + ACTION(U27_A8,"pin 26",U27)\ + ACTION(U27_CASH,"pin 28",U27)\ + ACTION(U27_CASL,"pin 29",U27)\ + ACTION(U27_RAS,"pin 14",U27)\ + ACTION(U27_WE,"pin 13",U27)\ + ACTION(U28,"U28/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U28_DQ0,"pin 2",U28)\ + ACTION(U28_DQ1,"pin 3",U28)\ + ACTION(U28_DQ2,"pin 4",U28)\ + ACTION(U28_DQ3,"pin 5",U28)\ + ACTION(U28_DQ4,"pin 7",U28)\ + ACTION(U28_DQ5,"pin 8",U28)\ + ACTION(U28_DQ6,"pin 9",U28)\ + ACTION(U28_DQ7,"pin 10",U28)\ + ACTION(U28_DQ8,"pin 31",U28)\ + ACTION(U28_DQ9,"pin 32",U28)\ + ACTION(U28_DQ10,"pin 33",U28)\ + ACTION(U28_DQ11,"pin 34",U28)\ + ACTION(U28_DQ12,"pin 36",U28)\ + ACTION(U28_DQ13,"pin 37",U28)\ + ACTION(U28_DQ14,"pin 38",U28)\ + ACTION(U28_DQ15,"pin 39",U28)\ + ACTION(U28_A0,"pin 16",U28)\ + ACTION(U28_A1,"pin 17",U28)\ + ACTION(U28_A2,"pin 18",U28)\ + ACTION(U28_A3,"pin 19",U28)\ + ACTION(U28_A4,"pin 22",U28)\ + ACTION(U28_A5,"pin 23",U28)\ + ACTION(U28_A6,"pin 24",U28)\ + ACTION(U28_A7,"pin 25",U28)\ + ACTION(U28_A8,"pin 26",U28)\ + ACTION(U28_CASH,"pin 28",U28)\ + ACTION(U28_CASL,"pin 29",U28)\ + ACTION(U28_RAS,"pin 14",U28)\ + ACTION(U28_WE,"pin 13",U28)\ + ACTION(U29,"U29/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U29_DQ0,"pin 2",U29)\ + ACTION(U29_DQ1,"pin 3",U29)\ + ACTION(U29_DQ2,"pin 4",U29)\ + ACTION(U29_DQ3,"pin 5",U29)\ + ACTION(U29_DQ4,"pin 7",U29)\ + ACTION(U29_DQ5,"pin 8",U29)\ + ACTION(U29_DQ6,"pin 9",U29)\ + ACTION(U29_DQ7,"pin 10",U29)\ + ACTION(U29_DQ8,"pin 31",U29)\ + ACTION(U29_DQ9,"pin 32",U29)\ + ACTION(U29_DQ10,"pin 33",U29)\ + ACTION(U29_DQ11,"pin 34",U29)\ + ACTION(U29_DQ12,"pin 36",U29)\ + ACTION(U29_DQ13,"pin 37",U29)\ + ACTION(U29_DQ14,"pin 38",U29)\ + ACTION(U29_DQ15,"pin 39",U29)\ + ACTION(U29_A0,"pin 16",U29)\ + ACTION(U29_A1,"pin 17",U29)\ + ACTION(U29_A2,"pin 18",U29)\ + ACTION(U29_A3,"pin 19",U29)\ + ACTION(U29_A4,"pin 22",U29)\ + ACTION(U29_A5,"pin 23",U29)\ + ACTION(U29_A6,"pin 24",U29)\ + ACTION(U29_A7,"pin 25",U29)\ + ACTION(U29_A8,"pin 26",U29)\ + ACTION(U29_CASH,"pin 28",U29)\ + ACTION(U29_CASL,"pin 29",U29)\ + ACTION(U29_RAS,"pin 14",U29)\ + ACTION(U29_WE,"pin 13",U29)\ + ACTION(U30,"U30/RAM (back left)",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(U30_DQ0,"pin 2",U30)\ + ACTION(U30_DQ1,"pin 3",U30)\ + ACTION(U30_DQ2,"pin 4",U30)\ + ACTION(U30_DQ3,"pin 5",U30)\ + ACTION(U30_DQ4,"pin 7",U30)\ + ACTION(U30_DQ5,"pin 8",U30)\ + ACTION(U30_DQ6,"pin 9",U30)\ + ACTION(U30_DQ7,"pin 10",U30)\ + ACTION(U30_DQ8,"pin 31",U30)\ + ACTION(U30_DQ9,"pin 32",U30)\ + ACTION(U30_DQ10,"pin 33",U30)\ + ACTION(U30_DQ11,"pin 34",U30)\ + ACTION(U30_DQ12,"pin 36",U30)\ + ACTION(U30_DQ13,"pin 37",U30)\ + ACTION(U30_DQ14,"pin 38",U30)\ + ACTION(U30_DQ15,"pin 39",U30)\ + ACTION(U30_A0,"pin 16",U30)\ + ACTION(U30_A1,"pin 17",U30)\ + ACTION(U30_A2,"pin 18",U30)\ + ACTION(U30_A3,"pin 19",U30)\ + ACTION(U30_A4,"pin 22",U30)\ + ACTION(U30_A5,"pin 23",U30)\ + ACTION(U30_A6,"pin 24",U30)\ + ACTION(U30_A7,"pin 25",U30)\ + ACTION(U30_A8,"pin 26",U30)\ + ACTION(U30_CASH,"pin 28",U30)\ + ACTION(U30_CASL,"pin 29",U30)\ + ACTION(U30_RAS,"pin 14",U30)\ + ACTION(U30_WE,"pin 13",U30)\ + ACTION(RA10,"RA10/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA10_1,"pin 1-2",RA10)\ + ACTION(RA10_2,"pin 3-4",RA10)\ + ACTION(RA10_3,"pin 5-6",RA10)\ + ACTION(RA10_4,"pin 7-8",RA10)\ + ACTION(RA11,"RA11/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA11_1,"pin 1-2",RA11)\ + ACTION(RA11_2,"pin 3-4",RA11)\ + ACTION(RA11_3,"pin 5-6",RA11)\ + ACTION(RA11_4,"pin 7-8",RA11)\ + ACTION(RA12,"RA12/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA12_1,"pin 1-2",RA12)\ + ACTION(RA12_2,"pin 3-4",RA12)\ + ACTION(RA12_3,"pin 5-6",RA12)\ + ACTION(RA12_4,"pin 7-8",RA12)\ + ACTION(RA13,"RA13/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA13_1,"pin 1-2",RA13)\ + ACTION(RA13_2,"pin 3-4",RA13)\ + ACTION(RA13_3,"pin 5-6",RA13)\ + ACTION(RA13_4,"pin 7-8",RA13)\ + /* /!\ TT_TDATA list need to stay in this order*/ \ + ACTION(TT_TDATA_R131,"R131",VOODOO_BOARD)\ + ACTION(TT_TDATA_R134,"R134",VOODOO_BOARD)\ + ACTION(TT_TDATA_R132,"R132",VOODOO_BOARD)\ + ACTION(TT_TDATA_R135,"R135",VOODOO_BOARD)\ + ACTION(TT_TDATA_R133,"R133",VOODOO_BOARD)\ + ACTION(TT_TDATA_R136,"R136",VOODOO_BOARD)\ + ACTION(TT_TDATA_R127,"R127",VOODOO_BOARD)\ + ACTION(TT_TDATA_R137,"R137",VOODOO_BOARD)\ + ACTION(TT_TDATA_R138,"R138",VOODOO_BOARD)\ + ACTION(TT_TDATA_R129,"R129",VOODOO_BOARD)\ + ACTION(TT_TDATA_R140,"R140",VOODOO_BOARD)\ + ACTION(TT_TDATA_R130,"R130",VOODOO_BOARD)\ + ACTION(TT_TDATA_R84,"R84",VOODOO_BOARD)\ + ACTION(TT_TDATA_R83,"R83",VOODOO_BOARD)\ + ACTION(TT_TDATA_R68,"R68",VOODOO_BOARD)\ + ACTION(TT_TDATA_R67,"R67",VOODOO_BOARD)\ + ACTION(RA31,"RA31/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA31_1,"pin 1-2",RA31)\ + ACTION(RA31_2,"pin 3-4",RA31)\ + ACTION(RA31_3,"pin 5-6",RA31)\ + ACTION(RA31_4,"pin 7-8",RA31)\ + ACTION(RA30,"RA30/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA30_1,"pin 1-2",RA30)\ + ACTION(RA30_2,"pin 3-4",RA30)\ + ACTION(RA30_3,"pin 5-6",RA30)\ + ACTION(RA30_4,"pin 7-8",RA30)\ + ACTION(R113,"R115",VOODOO_BOARD)\ + ACTION(RA25,"RA25/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA25_1,"pin 1-2",RA25)\ + ACTION(RA25_2,"pin 3-4",RA25)\ + ACTION(RA25_3,"pin 5-6",RA25)\ + ACTION(RA25_4,"pin 7-8",RA25)\ + ACTION(RA23,"RA23/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA23_1,"pin 1-2",RA23)\ + ACTION(RA23_2,"pin 3-4",RA23)\ + ACTION(RA23_3,"pin 5-6",RA23)\ + ACTION(RA23_4,"pin 7-8",RA23)\ + ACTION(R101,"R101",VOODOO_BOARD)\ + ACTION(RA29,"RA29/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA29_1,"pin 1-2",RA29)\ + ACTION(RA29_2,"pin 3-4",RA29)\ + ACTION(RA29_3,"pin 5-6",RA29)\ + ACTION(RA29_4,"pin 7-8",RA29)\ + ACTION(RA27,"RA27/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA27_1,"pin 1-2",RA27)\ + ACTION(RA27_2,"pin 3-4",RA27)\ + ACTION(RA27_3,"pin 5-6",RA27)\ + ACTION(RA27_4,"pin 7-8",RA27)\ + ACTION(R111,"R111",VOODOO_BOARD)\ + ACTION(RA20,"RA20/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA20_1,"pin 1-2",RA20)\ + ACTION(RA20_2,"pin 3-4",RA20)\ + ACTION(RA20_3,"pin 5-6",RA20)\ + ACTION(RA20_4,"pin 7-8",RA20)\ + ACTION(RA19,"RA19/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA19_1,"pin 1-2",RA19)\ + ACTION(RA19_2,"pin 3-4",RA19)\ + ACTION(RA19_3,"pin 5-6",RA19)\ + ACTION(RA19_4,"pin 7-8",RA19)\ + ACTION(R97,"R97",VOODOO_BOARD)\ + ACTION(RA32,"RA32/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA32_1,"pin 1-2",RA32)\ + ACTION(RA32_2,"pin 3-4",RA32)\ + ACTION(RA32_3,"pin 5-6",RA32)\ + ACTION(RA32_4,"pin 7-8",RA32)\ + ACTION(R115,"R115",VOODOO_BOARD)\ + ACTION(R150,"R150",VOODOO_BOARD)\ + ACTION(R114,"R114",VOODOO_BOARD)\ + ACTION(RA35,"RA35/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA35_1,"pin 1-2",RA35)\ + ACTION(RA35_2,"pin 3-4",RA35)\ + ACTION(RA35_3,"pin 5-6",RA35)\ + ACTION(RA35_4,"pin 7-8",RA35)\ + ACTION(RA34,"RA34/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA34_1,"pin 1-2",RA34)\ + ACTION(RA34_2,"pin 3-4",RA34)\ + ACTION(RA34_3,"pin 5-6",RA34)\ + ACTION(RA34_4,"pin 7-8",RA34)\ + ACTION(R116,"R116",VOODOO_BOARD)\ + ACTION(RA26,"RA26/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA26_1,"pin 1-2",RA26)\ + ACTION(RA26_2,"pin 3-4",RA26)\ + ACTION(RA26_3,"pin 5-6",RA26)\ + ACTION(RA26_4,"pin 7-8",RA26)\ + ACTION(RA24,"RA24/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA24_1,"pin 1-2",RA24)\ + ACTION(RA24_2,"pin 3-4",RA24)\ + ACTION(RA24_3,"pin 5-6",RA24)\ + ACTION(RA24_4,"pin 7-8",RA24)\ + ACTION(R102,"R102",VOODOO_BOARD)\ + ACTION(RA33,"RA33/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA33_1,"pin 1-2",RA33)\ + ACTION(RA33_2,"pin 3-4",RA33)\ + ACTION(RA33_3,"pin 5-6",RA33)\ + ACTION(RA33_4,"pin 7-8",RA33)\ + ACTION(RA28,"RA28/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA28_1,"pin 1-2",RA28)\ + ACTION(RA28_2,"pin 3-4",RA28)\ + ACTION(RA28_3,"pin 5-6",RA28)\ + ACTION(RA28_4,"pin 7-8",RA28)\ + ACTION(R112,"R112",VOODOO_BOARD)\ + ACTION(RA22,"RA22/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA22_1,"pin 1-2",RA22)\ + ACTION(RA22_2,"pin 3-4",RA22)\ + ACTION(RA22_3,"pin 5-6",RA22)\ + ACTION(RA22_4,"pin 7-8",RA22)\ + ACTION(RA21,"RA21/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA21_1,"pin 1-2",RA21)\ + ACTION(RA21_2,"pin 3-4",RA21)\ + ACTION(RA21_3,"pin 5-6",RA21)\ + ACTION(RA21_4,"pin 7-8",RA21)\ + ACTION(R98,"R98",VOODOO_BOARD)\ + ACTION(RA36,"RA36/RPACK",VOODOO_BOARD)\ + /* /!\ Keep in-order, only appEND new fields */ \ + ACTION(RA36_1,"pin 1-2",RA36)\ + ACTION(RA36_2,"pin 3-4",RA36)\ + ACTION(RA36_3,"pin 5-6",RA36)\ + ACTION(RA36_4,"pin 7-8",RA36)\ + ACTION(R118,"R118",VOODOO_BOARD)\ + ACTION(R149,"R149",VOODOO_BOARD)\ + ACTION(R117,"R117",VOODOO_BOARD)\ + +#define GEN_FAULT_SOURCES_ENUMS(_NAME_,_LOC_,_PARRENT_) _NAME_, +#define GEN_FAULT_SOURCES_ARRAY(_NAME_,_LOC_,_PARRENT_) { .eThisFaultSource=_NAME_ ,.szName=#_NAME_,.szLoc=_LOC_,.eParrentFaultSource=_PARRENT_, .dScore=0.0}, + +typedef enum _def_eFaultSource{ + VOODOO_BOARD = 0, + FAULT_SOURCES(GEN_FAULT_SOURCES_ENUMS) + _INVALID_FAULT_SOURCE_ +}def_eFaultSource; +#define NB_FAULT_SOURCE _INVALID_FAULT_SOURCE_ + +typedef struct _def_sFaultSourceScoreRec{ + def_eFaultSource eThisFaultSource; + char *szName; + char *szLoc; + def_eFaultSource eParrentFaultSource; + double dScore; +}def_sFaultSourceScoreRec; + +extern def_sFaultSourceScoreRec ar_dFaultScores[NB_FAULT_SOURCE]; +extern def_sFaultSourceScoreRec ar_dFaultScores_sorted[NB_FAULT_SOURCE]; + +void FaultSource_Reset(); +void FaultSource_AddScore(def_eFaultSource eFaultSource, double dScore); +void FaultSource_Sort(); +void FaultSource_GetLoc(def_eFaultSource eFaultSource, char* loc); +void FaultSource_Display(); + + +void +WordBitFaultSet( const unsigned long ErrorMark, + const double dScore, + const def_eFaultSource eFaultSourceL, + const def_eFaultSource eFaultSourceH); + +void +QuartetBitFaultSet( const unsigned long ErrorMark, + const double dScore, + const def_eFaultSource eFaultSource); + + +inline void +MemChipDQFaultSet( const unsigned long ErrorMark, + const double dScore, + const def_eFaultSource eFaultSourceL, + const def_eFaultSource eFaultSourceH); + +inline void +TMUTexDataFaultSet( const unsigned long ErrorMark_w0w1, + const unsigned long ErrorMark_w2w3, + const double dScore, + const def_eFaultSource eTMUFaultSource); + + +inline void +TMUTexDataCtrlFaultSet( const unsigned long ErrorMark, + double dScore, + const def_eFaultSource eFaultSourceCASL, + const def_eFaultSource eFaultSourceCASH, + const def_eFaultSource eFaultSourceRAS, + const def_eFaultSource eFaultSourceWE + ); + +#endif //_DEF_FAULTSOURCES_H_ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..ba61dce --- /dev/null +++ b/Makefile @@ -0,0 +1,21 @@ + +CC=gcc +CFLAGS=-Wall -std=gnu99 -O6 -march=pentium3 -fomit-frame-pointer -funroll-loops \ + -fexpensive-optimizations -ffast-math -fno-strict-aliasing + +CFLAGS+=-I. -I/home/chacha/glide-test/glide2x/cvg/init -I/home/chacha/glide-test/glide2x/swlibs/newpci/pcilib -I/home/chacha/glide-test/glide2x/swlibs/fxmisc -I/home/chacha/glide-test/glide2x/cvg/incsrc -I/home/chacha/glide-test/glide2x/cvg/glide/src +CFLAGS+=-DCVG + +#LFLAGS=-llibglide -L/home/chacha/glide-test/glide2x/cvg/lib +LFLAGS=-lglide -L/home/chacha/glide-test/glide2x/cvg/lib + +OBJ=main.o FaultSources.o Utils.o Draw.o Test_Address.o Test_Data.o Test_Data_Huge.o + + +%.o: %.c + $(CC) -c -o $@ $< $(CFLAGS) + +V2MemTest : $(OBJ) + $(CC) -o $@ $(LFLAGS) $^ + +all: V2MemTest diff --git a/Readme.md b/Readme.md new file mode 100644 index 0000000..e69de29 diff --git a/Test_Address.c b/Test_Address.c new file mode 100644 index 0000000..19180c7 --- /dev/null +++ b/Test_Address.c @@ -0,0 +1,574 @@ +#include +#include +#include +#include <3dfx.h> +#include + +#include "FaultSources.h" +#include "Utils.h" +#include "Draw.h" + +#include "Test_Address.h" + +typedef struct _def_sTestAddress { + FxU32 u32Addr; + unsigned char nBank; // RAS0 and RAS1 (Front/Back) + unsigned char nColBit; + unsigned char nRowBit; +}def_sTestAddress; + +/* +static sst1DeviceInfoStruct devInfo; +static FxU32* sst; +static SstRegs *sstregs; +*/ + +unsigned long +RenderTestAddress( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const char ucNumTMU, + const unsigned char RamSizeMB) +{ + devInfo->tmuInit0[(int)ucNumTMU] = SST_TREXINIT0_DEFAULT ; + + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + /* + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, 0x5000 | (devInfo->tmuInit0[(int)ucNumTMU] & ~0x7000)); + sst1InitIdle(sst); + */ + + // set downstream TMUs to passthrough + for (int i=0; itextureMode, SST_TC_PASS | SST_TCA_PASS); + + unsigned long NbErr=0; + //long TestVal1; + //long TestVal2; + //long TestValBlank1; + //long TestValBlank2; + + const def_sTestAddress add_list[] = + { + // Bank0 + {0x000000,0,0,0}, + /* not addressable because its a 64bit bus + {0x000001,0,0,0,0} + {0x000002,0,0,0,0} + {0x000004,0,0,0,0} + */ + {0x000008,0,1,0}, + {0x000010,0,2,0}, {0x000018,0,2,0}, // target + adjacent pin + {0x000020,0,3,0}, {0x000030,0,3,0}, + {0x000040,0,4,0}, {0x000060,0,4,0}, + {0x000080,0,5,0}, {0x0000C0,0,5,0}, + {0x000100,0,6,0}, {0x000180,0,6,0}, + {0x000200,0,7,0}, {0x000300,0,7,0}, + {0x000400,0,8,0}, {0x000600,0,8,0}, + {0x000800,0,9,0}, {0x000C00,0,9,0}, // => Ignoring adjacent for now + {0x001000,0,0,1}, {0x001800,0,0,1}, // It seems useless + {0x002000,0,0,2}, {0x003000,0,0,2}, + {0x004000,0,0,3}, {0x006000,0,0,3}, + {0x008000,0,0,4}, {0x00C000,0,0,4}, + {0x010000,0,0,5}, {0x018000,0,0,5}, + {0x020000,0,0,6}, {0x030000,0,0,6}, + {0x040000,0,0,7}, {0x060000,0,0,7}, + {0x080000,0,0,8}, {0x0C0000,0,0,8}, + {0x100000,0,0,9}, {0x180000,0,0,9}, + + // Bank1 + {0x200000,1,0,0}, + /* not addressable because its a 64bit bus + {0x200001,0,0,0,0} + {0x200002,0,0,0,0} + {0x200004,0,0,0,0} + */ + {0x200008,1,1,0}, + {0x200010,1,2,0}, {0x200018,1,2,0}, + {0x200020,1,3,0}, {0x200030,1,3,0}, + {0x200040,1,4,0}, {0x200060,1,4,0}, + {0x200080,1,5,0}, {0x2000C0,1,5,0}, + {0x200100,1,6,0}, {0x200180,1,6,0}, + {0x200200,1,7,0}, {0x200300,1,7,0}, + {0x200400,1,8,0}, {0x200600,1,8,0}, + {0x200800,1,9,0}, {0x200C00,1,9,0}, + {0x201000,1,0,1}, {0x201800,1,0,1}, + {0x202000,1,0,2}, {0x203000,1,0,2}, + {0x204000,1,0,3}, {0x206000,1,0,3}, + {0x208000,1,0,4}, {0x20C000,1,0,4}, + {0x210000,1,0,5}, {0x218000,1,0,5}, + {0x220000,1,0,6}, {0x230000,1,0,6}, + {0x240000,1,0,7}, {0x260000,1,0,7}, + {0x280000,1,0,8}, {0x2C0000,1,0,8}, + {0x300000,1,0,9}, {0x380000,1,0,9}, + }; + + for(unsigned char idx=0; + idx < sizeof(add_list)/sizeof(def_sTestAddress); + idx++) + { + if(RamSizeMB<4 && add_list[idx].u32Addr >= 0x300000) continue; + if(RamSizeMB<3 && add_list[idx].u32Addr >= 0x200000) continue; + if(RamSizeMB<2 && add_list[idx].u32Addr >= 0x100000) continue; + + const FxU32 TestVal1 = get_notnull_random_balanced_mByte(); + const FxU32 TestVal2 = get_notnull_random_balanced_mByte(); + const FxU32 TestValBlank1 = get_notnull_random_balanced_mByte(); + const FxU32 TestValBlank2 = get_notnull_random_balanced_mByte(); + + // Clearing memory targets + for(unsigned char idxclr=0; + idxclr < sizeof(add_list)/sizeof(def_sTestAddress); + idxclr++) + { + if(RamSizeMB<4 && add_list[idxclr].u32Addr >= 0x300000) continue; + if(RamSizeMB<3 && add_list[idxclr].u32Addr >= 0x200000) continue; + if(RamSizeMB<2 && add_list[idxclr].u32Addr >= 0x100000) continue; + + /* set to mem addr */ + ISET(sstregs->texBaseAddr, (add_list[idxclr].u32Addr>>3)); + /* First line, using bits 00..31*/ + volatile const FxU32 *texAddrBlank = (ucNumTMU<<(21-2)) + (((FxU32)0/*LOD0*/)<<(17-2)) + (FxU32 *)SST_TEX_ADDRESS(sst); + ISET(texAddrBlank[0], TestValBlank1); /* write a value */ + /* Second line, to use bits 32..63*/ + volatile const FxU32 *texAddrBlank2 = (ucNumTMU<<(21-2)) + (((FxU32)0/*LOD0*/)<<(17-2)) + (1<<(9-2))+ (FxU32 *)SST_TEX_ADDRESS(sst); + ISET(texAddrBlank2[0], TestValBlank2); /* write a value */ + } + + /* set to mem addr */ + ISET(sstregs->texBaseAddr, (add_list[idx].u32Addr>>3)); + /* First line, using bits 00..31*/ + volatile const FxU32 *texAddr = (ucNumTMU<<(21-2)) + (((FxU32)0/*LOD0*/)<<(17-2)) + (FxU32 *)SST_TEX_ADDRESS(sst); + ISET(texAddr[0], TestVal1); /* write a value */ + /* Second line, to use bits 32..63*/ + volatile const FxU32 *texAddr2 = (ucNumTMU<<(21-2)) + (((FxU32)0/*LOD0*/)<<(17-2)) + (1<<(9-2))+ (FxU32 *)SST_TEX_ADDRESS(sst); + ISET(texAddr2[0], TestVal2); /* write a value */ + + // Checking expected memory map is there + for(unsigned char idxdraw=0; + idxdraw < sizeof(add_list) / sizeof(def_sTestAddress); + idxdraw++) + { + if(RamSizeMB<4 && add_list[idxdraw].u32Addr >= 0x300000) continue; + if(RamSizeMB<3 && add_list[idxdraw].u32Addr >= 0x200000) continue; + if(RamSizeMB<2 && add_list[idxdraw].u32Addr >= 0x100000) continue; + + // testing copy beyond tested bit is useless & can raise + // false positive + if(idxdraw > idx) break; + + /* set to mem addr */ + ISET(sstregs->texBaseAddr, (add_list[idxdraw].u32Addr >> 3)); + drawTriangle(sstregs, 0, 0, 4); /* draw a 4x4 triangle */ + + // First line, to use bits 00..31 + const FxU32 L1 = IGET(sst[(SST_LFB_ADDR>>2) + 0]); + // Second line,to use bits 32..63 + const FxU32 L2 = IGET(sst[(SST_LFB_ADDR>>2) + (2048>>2) + 0]); + + const unsigned long ErrorMark_L1 = (idxdraw == idx) ? (L1 ^ TestVal1) : (L1 ^ TestValBlank1); + const unsigned long ErrorMark_L2 = (idxdraw == idx) ? (L2 ^ TestVal2) : (L2 ^ TestValBlank2); + + const unsigned long ErrorMarkBlank_L1 = (idxdraw == idx) ? (L1 ^ TestValBlank1) : (L1 ^ TestVal1); + const unsigned long ErrorMarkBlank_L2 = (idxdraw == idx) ? (L2 ^ TestValBlank2) : (L2 ^ TestVal2) ; + + if(ErrorMark_L1 || ErrorMark_L2) + { + const def_eFaultSource TMUTexADDR_0_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_0_0 : U8_TMU1_TEX_ADDR_0_0; + const def_eFaultSource TMUTexADDR_1_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_1_0 : U8_TMU1_TEX_ADDR_1_0; + const def_eFaultSource TMUTexADDR_2_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_2_0 : U8_TMU1_TEX_ADDR_2_0; + const def_eFaultSource TMUTexADDR_3_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_3_0 : U8_TMU1_TEX_ADDR_3_0; + const def_eFaultSource TMUTexWE = (ucNumTMU == 0) ? U9_TMU0_TEX_WE : U8_TMU1_TEX_WE; + const def_eFaultSource TMUTexCAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS0 : U8_TMU1_TEX_CAS0; + const def_eFaultSource TMUTexCAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS1 : U8_TMU1_TEX_CAS1; + const def_eFaultSource TMUTexCAS2 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS2 : U8_TMU1_TEX_CAS2; + const def_eFaultSource TMUTexCAS3 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS3 : U8_TMU1_TEX_CAS3; + const def_eFaultSource _TMUTexRAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS0 : U8_TMU1_TEX_RAS0; + const def_eFaultSource _TMUTexRAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS1 : U8_TMU1_TEX_RAS1; + const def_eFaultSource TMUTexRASCurrent = (add_list[idxdraw].nBank == 0) ? _TMUTexRAS0 : _TMUTexRAS1; + const def_eFaultSource _MEMChip_B0_0_A0 = (ucNumTMU == 0) ? U14_A0 : U13_A0; + const def_eFaultSource _MEMChip_B0_1_A0 = (ucNumTMU == 0) ? U12_A0 : U11_A0; + const def_eFaultSource _MEMChip_B0_2_A0 = (ucNumTMU == 0) ? U18_A0 : U16_A0; + const def_eFaultSource _MEMChip_B0_3_A0 = (ucNumTMU == 0) ? U17_A0 : U15_A0; + const def_eFaultSource _MEMChip_B1_0_A0 = (ucNumTMU == 0) ? U23_A0 : U27_A0; + const def_eFaultSource _MEMChip_B1_1_A0 = (ucNumTMU == 0) ? U24_A0 : U28_A0; + const def_eFaultSource _MEMChip_B1_2_A0 = (ucNumTMU == 0) ? U25_A0 : U29_A0; + const def_eFaultSource _MEMChip_B1_3_A0 = (ucNumTMU == 0) ? U26_A0 : U30_A0; + const def_eFaultSource MEMChip_0_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_A0 : _MEMChip_B1_0_A0; + const def_eFaultSource MEMChip_1_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_A0 : _MEMChip_B1_1_A0; + const def_eFaultSource MEMChip_2_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_A0 : _MEMChip_B1_2_A0; + const def_eFaultSource MEMChip_3_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_A0 : _MEMChip_B1_3_A0; + + const def_eFaultSource _MEMChip_B0_0_CASL = (ucNumTMU == 0) ? U14_CASL : U13_CASL; + const def_eFaultSource _MEMChip_B0_1_CASL = (ucNumTMU == 0) ? U12_CASL : U11_CASL; + const def_eFaultSource _MEMChip_B0_2_CASL = (ucNumTMU == 0) ? U18_CASL : U16_CASL; + const def_eFaultSource _MEMChip_B0_3_CASL = (ucNumTMU == 0) ? U17_CASL : U15_CASL; + const def_eFaultSource _MEMChip_B1_0_CASL = (ucNumTMU == 0) ? U23_CASL : U27_CASL; + const def_eFaultSource _MEMChip_B1_1_CASL = (ucNumTMU == 0) ? U24_CASL : U28_CASL; + const def_eFaultSource _MEMChip_B1_2_CASL = (ucNumTMU == 0) ? U25_CASL : U29_CASL; + const def_eFaultSource _MEMChip_B1_3_CASL = (ucNumTMU == 0) ? U26_CASL : U30_CASL; + const def_eFaultSource MEMChip_0_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_CASL : _MEMChip_B1_0_CASL; + const def_eFaultSource MEMChip_1_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_CASL : _MEMChip_B1_1_CASL; + const def_eFaultSource MEMChip_2_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_CASL : _MEMChip_B1_2_CASL; + const def_eFaultSource MEMChip_3_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_CASL : _MEMChip_B1_3_CASL; + + const def_eFaultSource _MEMChip_B0_0_CASH = (ucNumTMU == 0) ? U14_CASH : U13_CASH; + const def_eFaultSource _MEMChip_B0_1_CASH = (ucNumTMU == 0) ? U12_CASH : U11_CASH; + const def_eFaultSource _MEMChip_B0_2_CASH = (ucNumTMU == 0) ? U18_CASH : U16_CASH; + const def_eFaultSource _MEMChip_B0_3_CASH = (ucNumTMU == 0) ? U17_CASH : U15_CASH; + const def_eFaultSource _MEMChip_B1_0_CASH = (ucNumTMU == 0) ? U23_CASH : U27_CASH; + const def_eFaultSource _MEMChip_B1_1_CASH = (ucNumTMU == 0) ? U24_CASH : U28_CASH; + const def_eFaultSource _MEMChip_B1_2_CASH = (ucNumTMU == 0) ? U25_CASH : U29_CASH; + const def_eFaultSource _MEMChip_B1_3_CASH = (ucNumTMU == 0) ? U26_CASH : U30_CASH; + const def_eFaultSource MEMChip_0_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_CASH : _MEMChip_B1_0_CASH; + const def_eFaultSource MEMChip_1_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_CASH : _MEMChip_B1_1_CASH; + const def_eFaultSource MEMChip_2_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_CASH : _MEMChip_B1_2_CASH; + const def_eFaultSource MEMChip_3_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_CASH : _MEMChip_B1_3_CASH; + + const def_eFaultSource _MEMChip_B0_0_RAS = (ucNumTMU == 0) ? U14_RAS : U13_RAS; + const def_eFaultSource _MEMChip_B0_1_RAS = (ucNumTMU == 0) ? U12_RAS : U11_RAS; + const def_eFaultSource _MEMChip_B0_2_RAS = (ucNumTMU == 0) ? U18_RAS : U16_RAS; + const def_eFaultSource _MEMChip_B0_3_RAS = (ucNumTMU == 0) ? U17_RAS : U15_RAS; + const def_eFaultSource _MEMChip_B1_0_RAS = (ucNumTMU == 0) ? U23_RAS : U27_RAS; + const def_eFaultSource _MEMChip_B1_1_RAS = (ucNumTMU == 0) ? U24_RAS : U28_RAS; + const def_eFaultSource _MEMChip_B1_2_RAS = (ucNumTMU == 0) ? U25_RAS : U29_RAS; + const def_eFaultSource _MEMChip_B1_3_RAS = (ucNumTMU == 0) ? U26_RAS : U30_RAS; + const def_eFaultSource MEMChip_0_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_RAS : _MEMChip_B1_0_RAS; + const def_eFaultSource MEMChip_1_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_RAS : _MEMChip_B1_1_RAS; + const def_eFaultSource MEMChip_2_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_RAS : _MEMChip_B1_2_RAS; + const def_eFaultSource MEMChip_3_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_RAS : _MEMChip_B1_3_RAS; + + const def_eFaultSource _MEMChip_B0_0_WE = (ucNumTMU == 0) ? U14_WE : U13_WE; + const def_eFaultSource _MEMChip_B0_1_WE = (ucNumTMU == 0) ? U12_WE : U11_WE; + const def_eFaultSource _MEMChip_B0_2_WE = (ucNumTMU == 0) ? U18_WE : U16_WE; + const def_eFaultSource _MEMChip_B0_3_WE = (ucNumTMU == 0) ? U17_WE : U15_WE; + const def_eFaultSource _MEMChip_B1_0_WE = (ucNumTMU == 0) ? U23_WE : U27_WE; + const def_eFaultSource _MEMChip_B1_1_WE = (ucNumTMU == 0) ? U24_WE : U28_WE; + const def_eFaultSource _MEMChip_B1_2_WE = (ucNumTMU == 0) ? U25_WE : U29_WE; + const def_eFaultSource _MEMChip_B1_3_WE = (ucNumTMU == 0) ? U26_WE : U30_WE; + const def_eFaultSource MEMChip_0_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_WE : _MEMChip_B1_0_WE; + const def_eFaultSource MEMChip_1_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_WE : _MEMChip_B1_1_WE; + const def_eFaultSource MEMChip_2_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_WE : _MEMChip_B1_2_WE; + const def_eFaultSource MEMChip_3_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_WE : _MEMChip_B1_3_WE; + + const def_eFaultSource _RES_RAS0 = (ucNumTMU == 0) ? R118 : R115; + const def_eFaultSource _RES_RAS1 = (ucNumTMU == 0) ? R149 : R150; + const def_eFaultSource RES_RAS = (add_list[idxdraw].nBank == 0) ? _RES_RAS0 : _RES_RAS1; + const def_eFaultSource RES_CAS = (ucNumTMU == 0) ? RA36 : RA32; + const def_eFaultSource RES_WE = (ucNumTMU == 0) ? R117 : R114; + + const def_eFaultSource RES_TEXADDR_0_L = (ucNumTMU == 0) ? RA35 : RA31; + const def_eFaultSource RES_TEXADDR_0_H = (ucNumTMU == 0) ? RA34 : RA30; + const def_eFaultSource RES_TEXADDR_0_8 = (ucNumTMU == 0) ? R116 : R113; + const def_eFaultSource RES_TEXADDR_1_L = (ucNumTMU == 0) ? RA26 : RA25; + const def_eFaultSource RES_TEXADDR_1_H = (ucNumTMU == 0) ? RA24 : RA23; + const def_eFaultSource RES_TEXADDR_1_8 = (ucNumTMU == 0) ? R102 : R101; + const def_eFaultSource RES_TEXADDR_2_L = (ucNumTMU == 0) ? RA33 : RA29; + const def_eFaultSource RES_TEXADDR_2_H = (ucNumTMU == 0) ? RA28 : RA27; + const def_eFaultSource RES_TEXADDR_2_8 = (ucNumTMU == 0) ? R112 : R111; + const def_eFaultSource RES_TEXADDR_3_L = (ucNumTMU == 0) ? RA22 : RA20; + const def_eFaultSource RES_TEXADDR_3_H = (ucNumTMU == 0) ? RA21 : RA19; + const def_eFaultSource RES_TEXADDR_3_8 = (ucNumTMU == 0) ? R98 : R97; + + + if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 2) + { + NbErr++; + /* + printf("1: %08x %d\n", + ErrorMark_L1 & 0x0000FFFF, + count_bit32(ErrorMark_L1 & 0x0000FFFF));*/ + if((idxdraw == idx) && count_bit32(ErrorMark_L1 & 0x0000FFFF) > 6) + { + FaultSource_AddScore( TMUTexWE, 1.0/4); + FaultSource_AddScore( RES_WE, 1.0/4); + FaultSource_AddScore( MEMChip_0_WE, 1.0/1); + } + + if(count_bit32(ErrorMarkBlank_L1 & 0x0000FFFF) < 3) + { + if(add_list[idx].nColBit!=0) + { + FaultSource_AddScore( MEMChip_0_A0 + add_list[idx].nColBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_0_0 + add_list[idx].nColBit, 1.0/1); + if(add_list[idx].nColBit < 4) + FaultSource_AddScore( RES_TEXADDR_0_L + add_list[idx].nColBit + 1, 1.0/2); + else if(add_list[idx].nColBit < 8) + FaultSource_AddScore( RES_TEXADDR_0_H + add_list[idx].nColBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_0_8 + 1, 1.0/2); + } + + if(add_list[idx].nRowBit!=0) + { + FaultSource_AddScore( MEMChip_0_A0 + add_list[idx].nRowBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_0_0 + add_list[idx].nRowBit, 1.0/1); + if(add_list[idx].nRowBit < 4) + FaultSource_AddScore( RES_TEXADDR_0_L + add_list[idx].nRowBit + 1, 1.0/2); + else if(add_list[idx].nRowBit < 8) + FaultSource_AddScore( RES_TEXADDR_0_H + add_list[idx].nRowBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_0_8 + 1, 1.0/2); + } + } + else + { + FaultSource_AddScore( TMUTexRASCurrent, 1.0/8); + FaultSource_AddScore( RES_RAS, 1.0/8); + FaultSource_AddScore( MEMChip_0_RAS, 1.0/4); + + if(ErrorMark_L1 & 0x000000FF) + { + FaultSource_AddScore( TMUTexCAS0, 1.0/16); + FaultSource_AddScore( RES_CAS+1, 1.0/16); + FaultSource_AddScore( MEMChip_0_CASL, 1.0/8); + } + if(ErrorMark_L1 & 0x0000FF00) + { + FaultSource_AddScore( TMUTexCAS1, 1.0/16);; + FaultSource_AddScore( RES_CAS+2, 1.0/16); + FaultSource_AddScore( MEMChip_0_CASH, 1.0/8); + } + } + + } + + // Error only if more than 6/16 bits are in error + if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 2) + { + NbErr++;/* + printf("2: %08x %d\n", + ErrorMark_L1 & 0xFFFF0000, + count_bit32(ErrorMark_L1 & 0xFFFF0000));*/ + if((idxdraw == idx) && count_bit32(ErrorMark_L1 & 0xFFFF0000) > 6) + { + FaultSource_AddScore( TMUTexWE, 1.0/4); + FaultSource_AddScore( RES_WE, 1.0/4); + FaultSource_AddScore( MEMChip_1_WE, 1.0/1); + } + if(count_bit32(ErrorMarkBlank_L1 & 0xFFFF0000) < 3) + { + if(add_list[idx].nColBit!=0) + { + FaultSource_AddScore( MEMChip_1_A0 + add_list[idx].nColBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_1_0 + add_list[idx].nColBit, 1.0/1); + if(add_list[idx].nColBit < 4) + FaultSource_AddScore( RES_TEXADDR_1_L + add_list[idx].nColBit + 1, 1.0/2); + else if(add_list[idx].nColBit < 8) + FaultSource_AddScore( RES_TEXADDR_1_H + add_list[idx].nColBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_1_8 + 1, 1.0/2); + } + + if(add_list[idx].nRowBit!=0) + { + FaultSource_AddScore( MEMChip_1_A0 + add_list[idx].nRowBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_1_0 + add_list[idx].nRowBit, 1.0/1); + if(add_list[idx].nRowBit < 4) + FaultSource_AddScore( RES_TEXADDR_1_L + add_list[idx].nRowBit + 1, 1.0/2); + else if(add_list[idx].nRowBit < 8) + FaultSource_AddScore( RES_TEXADDR_1_H + add_list[idx].nRowBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_1_8 + 1, 1.0/2); + } + } + else + { + FaultSource_AddScore( TMUTexRASCurrent, 1.0/8); + FaultSource_AddScore( RES_RAS, 1.0/8); + FaultSource_AddScore( MEMChip_1_RAS, 1.0/4); + + if(ErrorMark_L1 & 0x00FF0000) + { + FaultSource_AddScore( TMUTexCAS0, 1.0/16); + FaultSource_AddScore( RES_CAS+1, 1.0/16); + FaultSource_AddScore( MEMChip_1_CASL, 1.0/8); + } + + if(ErrorMark_L1 & 0xFF000000) + { + FaultSource_AddScore( TMUTexCAS1, 1.0/16); + FaultSource_AddScore( RES_CAS+2, 1.0/16); + FaultSource_AddScore( MEMChip_1_CASH, 1.0/8); + } + } + } + + if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 2) + { + NbErr++;/* + printf("3: %08x %d\n", + ErrorMark_L2 & 0x0000FFFF, + count_bit32(ErrorMark_L2 & 0x0000FFFF));*/ + if((idxdraw == idx) && count_bit32(ErrorMark_L2 & 0x0000FFFF) > 6) + { + FaultSource_AddScore( TMUTexWE, 1.0/4); + FaultSource_AddScore( RES_WE, 1.0/4); + FaultSource_AddScore( MEMChip_2_WE, 1.0); + } + + if(count_bit32(ErrorMarkBlank_L2 & 0x0000FFFF) < 3) + { + if(add_list[idx].nColBit!=0) + { + FaultSource_AddScore( MEMChip_2_A0 + add_list[idx].nColBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_2_0 + add_list[idx].nColBit, 1.0/1); + if(add_list[idx].nColBit < 4) + FaultSource_AddScore( RES_TEXADDR_2_L + add_list[idx].nColBit + 1, 1.0/2); + else if(add_list[idx].nColBit < 8) + FaultSource_AddScore( RES_TEXADDR_2_H + add_list[idx].nColBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_2_8 + 1, 1.0/2); + } + + if(add_list[idx].nRowBit!=0) + { + FaultSource_AddScore( MEMChip_2_A0 + add_list[idx].nRowBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_2_0 + add_list[idx].nRowBit, 1.0/1); + if(add_list[idx].nRowBit < 4) + FaultSource_AddScore( RES_TEXADDR_2_L + add_list[idx].nRowBit + 1, 1.0/2); + else if(add_list[idx].nRowBit < 8) + FaultSource_AddScore( RES_TEXADDR_2_H + add_list[idx].nRowBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_2_8 + 1, 1.0/2); + } + } + else + { + FaultSource_AddScore( TMUTexRASCurrent, 1.0/8); + FaultSource_AddScore( RES_RAS, 1.0/8); + FaultSource_AddScore( MEMChip_2_RAS, 1.0/4); + + if(ErrorMark_L2 & 0x000000FF) + { + FaultSource_AddScore( TMUTexCAS2, 1.0/16); + FaultSource_AddScore( RES_CAS+3, 1.0/16); + FaultSource_AddScore( MEMChip_2_CASL, 1.0/8); + } + + if(ErrorMark_L2 & 0x0000FF00) + { + FaultSource_AddScore( TMUTexCAS3, 1.0/16); + FaultSource_AddScore( RES_CAS+4, 1.0/16); + FaultSource_AddScore( MEMChip_2_CASH, 1.0/8); + } + } + } + + if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 2) + { + NbErr++;/* + printf("4: %08x %d\n", + ErrorMark_L2 & 0xFFFF0000, + count_bit32(ErrorMark_L2 & 0xFFFF0000));*/ + if((idxdraw == idx) && count_bit32(ErrorMark_L2 & 0xFFFF0000) > 6) + { + FaultSource_AddScore( TMUTexWE, 1.0/4); + FaultSource_AddScore( RES_WE, 1.0/4); + FaultSource_AddScore( MEMChip_3_WE, 1.0); + } + + if(count_bit32(ErrorMarkBlank_L2 & 0xFFFF0000) < 3) + { + if(add_list[idx].nColBit!=0) + { + FaultSource_AddScore( MEMChip_3_A0 + add_list[idx].nColBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_3_0 + add_list[idx].nColBit, 1.0/1); + if(add_list[idx].nColBit < 4) + FaultSource_AddScore( RES_TEXADDR_3_L + add_list[idx].nColBit + 1, 1.0/2); + else if(add_list[idx].nColBit < 8) + FaultSource_AddScore( RES_TEXADDR_3_H + add_list[idx].nColBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_3_8 + 1, 1.0/2); + } + + if(add_list[idx].nRowBit!=0) + { + FaultSource_AddScore( MEMChip_3_A0 + add_list[idx].nRowBit, 1.0/1); + FaultSource_AddScore( TMUTexADDR_3_0 + add_list[idx].nRowBit, 1.0/1); + if(add_list[idx].nRowBit < 4) + FaultSource_AddScore( RES_TEXADDR_3_L + add_list[idx].nRowBit + 1, 1.0/2); + else if(add_list[idx].nRowBit < 8) + FaultSource_AddScore( RES_TEXADDR_3_H + add_list[idx].nRowBit + 1, 1.0/2); + else + FaultSource_AddScore( RES_TEXADDR_3_8 + 1, 1.0/2); + } + } + else + { + FaultSource_AddScore( TMUTexRASCurrent, 1.0/8); + FaultSource_AddScore( RES_RAS, 1.0/8); + FaultSource_AddScore( MEMChip_3_RAS, 1.0/4); + + if(ErrorMark_L2 & 0x00FF0000) + { + FaultSource_AddScore( TMUTexCAS2, 1.0/16); + FaultSource_AddScore( RES_CAS+3, 1.0/16); + FaultSource_AddScore( MEMChip_3_CASL, 1.0/8); + } + + if(ErrorMark_L2 & 0xFF000000) + { + FaultSource_AddScore( TMUTexCAS3, 1.0/16); + FaultSource_AddScore( RES_CAS+4, 1.0/16); + FaultSource_AddScore( MEMChip_3_CASH, 1.0/8); + } + } + + } + /* + if(idxdraw == idx) + { + if(ErrorMark_L1) + { + printf("E (31..00): @%08x, read %08x, expected %08x !\n" , + add_list[idxdraw].u32Addr, + L1 , + TestVal1); + } + if(ErrorMark_L2) + { + printf("E (63..32): @%08x, read %08x, expected %08x !\n" , + add_list[idxdraw].u32Addr, + L2 , + TestVal2); + } + } + else + { + if(ErrorMark_L1) + { + printf("E (31..00)(trash) : @%08x, read %08x, expected %08x !\n" , + add_list[idxdraw].u32Addr, + L1 , + TestValBlank1); + } + if(ErrorMark_L2) + { + printf("E (63..32)(trash) : @%08x, read %08x, expected %08x !\n" , + add_list[idxdraw].u32Addr, + L2 , + TestValBlank2); + } + } + + if(!ErrorMark_L1 && !ErrorMark_L2) + { + printf("OK !!\n"); + } + */ + + + //printf("@ %08x done\n",add_list[idx]); + } + + } + } + sst1InitIdle(sst); + ISET(SST_TREX(sst,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + return NbErr; +} diff --git a/Test_Address.h b/Test_Address.h new file mode 100644 index 0000000..f204c86 --- /dev/null +++ b/Test_Address.h @@ -0,0 +1,11 @@ +#ifndef _DEF_TEST_ADDRESS_H_ +#define _DEF_TEST_ADDRESS_H_ + +unsigned long +RenderTestAddress( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const char ucNumTMU, + const unsigned char RamSizeMB); + +#endif //_DEF_TEST_ADDRESS_H_ diff --git a/Test_Data.c b/Test_Data.c new file mode 100644 index 0000000..69d709c --- /dev/null +++ b/Test_Data.c @@ -0,0 +1,661 @@ +#include +#include +#include +#include <3dfx.h> +#include + +#include "FaultSources.h" +#include "Utils.h" +#include "Draw.h" + +#include "Test_Data.h" + +static unsigned long long +RenderTest( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const char ucNumTMU, + const FxU32 mem, + const FxU32 value1, + const FxU32 value2) +{ + + /* set the Init0 register to enable ? MBytes of memory */ + // info->tmuInit0[tmu] = SST_TREXINIT0_DEFAULT | BIT(20); // BIT(20) seems to use bank 2...even if TMU mem is <= 2MB + + devInfo->tmuInit0[(int)ucNumTMU] = SST_TREXINIT0_DEFAULT ; + + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + /* + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, 0x5000 | (devInfo->tmuInit0[(int)ucNumTMU] & ~0x7000)); + sst1InitIdle(sst); + */ + ISET(sstregs->texBaseAddr, (mem>>3)); /* set to mem addr */ + + // First line, to use bits 0..31 + volatile const FxU32 *texAddr = (ucNumTMU<<(21-2)) + (((FxU32)0)<<(17-2)) + (FxU32 *)SST_TEX_ADDRESS(sstregs); + ISET(texAddr[0], value1); /* write a value */ + ISET(texAddr[1], value1+1); /* write a value */ + ISET(texAddr[2], value1+2); /* write a value */ + ISET(texAddr[3], value1+3); /* write a value */ + + // Second line, to use bits 32..63 + volatile const FxU32 *texAddr2 = (ucNumTMU<<(21-2)) + (((FxU32)0)<<(17-2)) + (1<<(9-2))+ (FxU32 *)SST_TEX_ADDRESS(sstregs); + ISET(texAddr2[0], value2); /* write a value */ + ISET(texAddr2[1], value2+1); /* write a value */ + ISET(texAddr2[2], value2+2); /* write a value */ + ISET(texAddr2[3], value2+3); /* write a value */ + + drawTriangle(sstregs,0,0,10); /* draw a 10x10 triangle */ + + // First line pixels addresses + const FxU32 L1_1 = IGET(sst[(SST_LFB_ADDR>>2)+0]); + const FxU32 L1_2 = IGET(sst[(SST_LFB_ADDR>>2)+1]); + const FxU32 L1_3 = IGET(sst[(SST_LFB_ADDR>>2)+2]); + const FxU32 L1_4 = IGET(sst[(SST_LFB_ADDR>>2)+3]); + + // Second line pixels addresses + const FxU32 L2_1 = IGET(sst[(SST_LFB_ADDR>>2)+(2048>>2)+0]); + const FxU32 L2_2 = IGET(sst[(SST_LFB_ADDR>>2)+(2048>>2)+1]); + const FxU32 L2_3 = IGET(sst[(SST_LFB_ADDR>>2)+(2048>>2)+2]); + const FxU32 L2_4 = IGET(sst[(SST_LFB_ADDR>>2)+(2048>>2)+3]); + + unsigned long long NbErr = 0; + //unsigned char bErrLowBytes=0; + //unsigned char bErrHighBytes=0; + if( L1_1 != value1) + { + //printf("Error on pixel LFB[0][0] (0x%08x)!\n",mem); + NbErr++; + //bErrLowBytes=1; + } + if( L1_2 != value1+1) + { + //printf("Error on pixel LFB[0][1] (0x%08x)!\n",mem); + NbErr++; + //bErrLowBytes=1; + } + if( L1_3 != value1+2) + { + //printf("Error on pixel LFB[0][2] (0x%08x)!\n",mem); + NbErr++; + //bErrLowBytes=1; + } + if( L1_4 != value1+3) + { + //printf("Error on pixel LFB[0][3] (0x%08x)!\n",mem); + NbErr++; + //bErrLowBytes=1; + } + + if( L2_1 != value2) + { + //printf("Error on pixel LFB[1][0] (0x%08x)!\n",mem); + NbErr++; + //bErrHighBytes=1; + } + if( L2_2 != value2+1) + { + //printf("Error on pixel LFB[1][1] (0x%08x)!\n",mem); + NbErr++; + //bErrHighBytes=1; + } + if( L2_3 != value2+2) + { + //printf("Error on pixel LFB[1][2] (0x%08x)!\n",mem); + NbErr++; + //bErrHighBytes=1; + } + if( L2_4 != value2+3) + { + //printf("Error on pixel LFB[1][3] (0x%08x)!\n",mem); + NbErr++; + //bErrHighBytes=1; + } + + // Diag Help logs + + const unsigned long ErrorMark_L1_1 = L1_1 ^ ( value1 + 0 ); + const unsigned long ErrorMark_L1_2 = L1_2 ^ ( value1 + 1 ); + const unsigned long ErrorMark_L1_3 = L1_3 ^ ( value1 + 2 ); + const unsigned long ErrorMark_L1_4 = L1_4 ^ ( value1 + 3 ); + const unsigned long ErrorMark_L2_1 = L2_1 ^ ( value2 + 0 ); + const unsigned long ErrorMark_L2_2 = L2_2 ^ ( value2 + 1 ); + const unsigned long ErrorMark_L2_3 = L2_3 ^ ( value2 + 2 ); + const unsigned long ErrorMark_L2_4 = L2_4 ^ ( value2 + 3 ); + + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, U9_TMU0_TF_DATA_0, U9_TMU0_TF_DATA_0); + + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, TT_TDATA_R131, TT_TDATA_R131); + + QuartetBitFaultSet(ErrorMark_L1_1 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_1 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L1_2 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_2 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L1_3 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_3 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L1_4 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L1_4 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L2_1 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_1 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L2_2 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_2 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L2_3 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_3 >> 28, 1.0/16, RA13_1); + + QuartetBitFaultSet(ErrorMark_L2_4 >> 0, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 4, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 8, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 12, 1.0/16, RA13_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 16, 1.0/16, RA10_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 20, 1.0/16, RA11_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 24, 1.0/16, RA12_1); + QuartetBitFaultSet(ErrorMark_L2_4 >> 28, 1.0/16, RA13_1); + + const double dScoreFront = (mem >= 0x200000) ? 0.5/4 : 1.0/4; + const double dScoreBack = (mem >= 0x200000) ? 1.0/4 : 0.5/4; + + if(ucNumTMU == 0) + { + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + + MemChipDQFaultSet(ErrorMark_L1_1, dScoreFront, U14, U12); + MemChipDQFaultSet(ErrorMark_L1_2, dScoreFront, U14, U12); + MemChipDQFaultSet(ErrorMark_L1_3, dScoreFront, U14, U12); + MemChipDQFaultSet(ErrorMark_L1_4, dScoreFront, U14, U12); + + MemChipDQFaultSet(ErrorMark_L2_1, dScoreFront, U18, U17); + MemChipDQFaultSet(ErrorMark_L2_2, dScoreFront, U18, U17); + MemChipDQFaultSet(ErrorMark_L2_3, dScoreFront, U18, U17); + MemChipDQFaultSet(ErrorMark_L2_4, dScoreFront, U18, U17); + + MemChipDQFaultSet(ErrorMark_L1_1, dScoreBack, U23, U24); + MemChipDQFaultSet(ErrorMark_L1_2, dScoreBack, U23, U24); + MemChipDQFaultSet(ErrorMark_L1_3, dScoreBack, U23, U24); + MemChipDQFaultSet(ErrorMark_L1_4, dScoreBack, U23, U12); + + MemChipDQFaultSet(ErrorMark_L2_1, dScoreBack, U25, U26); + MemChipDQFaultSet(ErrorMark_L2_2, dScoreBack, U25, U26); + MemChipDQFaultSet(ErrorMark_L2_3, dScoreBack, U25, U26); + MemChipDQFaultSet(ErrorMark_L2_4, dScoreBack, U25, U26); + + TMUTexDataFaultSet(ErrorMark_L1_1, ErrorMark_L2_1, 1.0/4, U9_TMU0); + TMUTexDataFaultSet(ErrorMark_L1_2, ErrorMark_L2_2, 1.0/4, U9_TMU0); + TMUTexDataFaultSet(ErrorMark_L1_3, ErrorMark_L2_3, 1.0/4, U9_TMU0); + TMUTexDataFaultSet(ErrorMark_L1_4, ErrorMark_L2_4, 1.0/4, U9_TMU0); + + TMUTexDataCtrlFaultSet( ErrorMark_L1_1, + 1.0/4, + U9_TMU0_TEX_CAS0, + U9_TMU0_TEX_CAS1, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_2, + 1.0/4, + U9_TMU0_TEX_CAS0, + U9_TMU0_TEX_CAS1, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_3, + 1.0/4, + U9_TMU0_TEX_CAS0, + U9_TMU0_TEX_CAS1, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_4, + 1.0/4, + U9_TMU0_TEX_CAS0, + U9_TMU0_TEX_CAS1, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_1, + 1.0/4, + U9_TMU0_TEX_CAS2, + U9_TMU0_TEX_CAS3, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_2, + 1.0/4, + U9_TMU0_TEX_CAS2, + U9_TMU0_TEX_CAS3, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_3, + 1.0/4, + U9_TMU0_TEX_CAS2, + U9_TMU0_TEX_CAS3, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_4, + 1.0/4, + U9_TMU0_TEX_CAS2, + U9_TMU0_TEX_CAS3, + mem < 0x200000 ? U9_TMU0_TEX_RAS0 : U9_TMU0_TEX_RAS1, + U9_TMU0_TEX_WE); + + } + else if(ucNumTMU == 1) + { + /* during TMU1 test, TMU0 doesnt receive any textures => ignoring these + WordBitFaultSet(ErrorMark_L1_1, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 0.5, U9_TMU0_FT_DATA_0, U9_TMU0_FT_DATA_0); + */ + + // U9_TMU0_TT_DATA_x is only tested when using TMU1 + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, U9_TMU0_TT_DATA_0, U9_TMU0_TT_DATA_0); + + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, U8_TMU1_TF_DATA_0, U8_TMU1_TF_DATA_0); + + WordBitFaultSet(ErrorMark_L1_1, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_2, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_3, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L1_4, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_1, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_2, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_3, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + WordBitFaultSet(ErrorMark_L2_4, 1.0/16, U8_TMU1_FT_DATA_0, U8_TMU1_FT_DATA_0); + + MemChipDQFaultSet(ErrorMark_L1_1, dScoreFront, U13, U11); + MemChipDQFaultSet(ErrorMark_L1_2, dScoreFront, U13, U11); + MemChipDQFaultSet(ErrorMark_L1_3, dScoreFront, U13, U11); + MemChipDQFaultSet(ErrorMark_L1_4, dScoreFront, U13, U11); + + MemChipDQFaultSet(ErrorMark_L2_1, dScoreFront, U16, U15); + MemChipDQFaultSet(ErrorMark_L2_2, dScoreFront, U16, U15); + MemChipDQFaultSet(ErrorMark_L2_3, dScoreFront, U16, U15); + MemChipDQFaultSet(ErrorMark_L2_4, dScoreFront, U16, U15); + + MemChipDQFaultSet(ErrorMark_L1_1, dScoreBack, U27, U28); + MemChipDQFaultSet(ErrorMark_L1_2, dScoreBack, U27, U28); + MemChipDQFaultSet(ErrorMark_L1_3, dScoreBack, U27, U28); + MemChipDQFaultSet(ErrorMark_L1_4, dScoreBack, U27, U28); + + MemChipDQFaultSet(ErrorMark_L2_1, dScoreBack, U29, U30); + MemChipDQFaultSet(ErrorMark_L2_2, dScoreBack, U29, U30); + MemChipDQFaultSet(ErrorMark_L2_3, dScoreBack, U29, U30); + MemChipDQFaultSet(ErrorMark_L2_4, dScoreBack, U29, U30); + + TMUTexDataFaultSet(ErrorMark_L1_1, ErrorMark_L2_1, 1.0/4, U8_TMU1); + TMUTexDataFaultSet(ErrorMark_L1_2, ErrorMark_L2_2, 1.0/4, U8_TMU1); + TMUTexDataFaultSet(ErrorMark_L1_3, ErrorMark_L2_3, 1.0/4, U8_TMU1); + TMUTexDataFaultSet(ErrorMark_L1_4, ErrorMark_L2_4, 1.0/4, U8_TMU1); + + TMUTexDataCtrlFaultSet( ErrorMark_L1_1, + 1.0/4, + U8_TMU1_TEX_CAS0, + U8_TMU1_TEX_CAS1, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_2, + 1.0/4, + U8_TMU1_TEX_CAS0, + U8_TMU1_TEX_CAS1, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_3, + 1.0/4, + U8_TMU1_TEX_CAS0, + U8_TMU1_TEX_CAS1, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L1_4, + 1.0/4, + U8_TMU1_TEX_CAS0, + U8_TMU1_TEX_CAS1, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_1, + 1.0/4, + U8_TMU1_TEX_CAS2, + U8_TMU1_TEX_CAS3, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_2, + 1.0/4, + U8_TMU1_TEX_CAS2, + U8_TMU1_TEX_CAS3, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_3, + 1.0/4, + U8_TMU1_TEX_CAS2, + U8_TMU1_TEX_CAS3, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE); + TMUTexDataCtrlFaultSet( ErrorMark_L2_4, + 1.0/4, + U8_TMU1_TEX_CAS2, + U8_TMU1_TEX_CAS3, + mem < 0x200000 ? U8_TMU1_TEX_RAS0 : U8_TMU1_TEX_RAS1, + U8_TMU1_TEX_WE ); + } + + /* + if( NbErr ) + { + printf("============\n"); + if(L1_1 != value1+0) + { + printf( "LFB[0][0] is 0x%08x [expected 0x%08x] !\n", L1_1, value1+0); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L1_1, 31, 0); + printf( "\n"); + } + if(L1_2 != value1+1) + { + printf( "LFB[0][1] is 0x%08x [expected 0x%08x] !\n", L1_2, value1+1); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L1_2, 31, 0); + printf( "\n"); + } + if(L1_3 != value1+2) + { + printf( "LFB[0][2] is 0x%08x [expected 0x%08x] !\n", L1_3, value1+2); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L1_3, 31, 0); + printf( "\n"); + } + if(L1_4!= value1+3) + { + printf( "LFB[0][3] is 0x%08x [expected 0x%08x] !\n", L1_4, value1+3); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L1_4, 31, 0); + printf( "\n"); + } + + if(L2_1 != value2+0) + { + printf( "LFB[1][0] is 0x%08x [expected 0x%08x] !\n", L2_1, value2+0); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L2_1, 63, 21); + printf( "\n"); + } + if(L2_2 != value2+1) + { + printf( "LFB[1][1] is 0x%08x [expected 0x%08x] !\n", L2_2, value2+1); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L2_2, 63, 21); + printf( "\n"); + } + if(L2_3 != value2+2) + { + printf( "LFB[1][2] is 0x%08x [expected 0x%08x] !\n", L2_3, value2+2); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L2_3, 63, 21); + printf( "\n"); + } + if(L2_4!= value2+3) + { + printf( "LFB[1][3] is 0x%08x [expected 0x%08x] !\n", L2_4, value2+3); + printf( "Faulty bits :\n"); + printbin32Info(ErrorMark_L2_4, 63, 21); + printf( "\n"); + } + + if(bErrLowBytes) + { + if(tmu == 0) + { + if( (ErrorMark_L1_1 & 0xFFFF) + || (ErrorMark_L1_2 & 0xFFFF) + || (ErrorMark_L1_3 & 0xFFFF) + || (ErrorMark_L1_4 & 0xFFFF) ) + { + printf("Check DQ connections to/from U14 (front) and U23 (back)\n"); + } + + if( (ErrorMark_L1_1 & 0xFFFF0000) + || (ErrorMark_L1_2 & 0xFFFF0000) + || (ErrorMark_L1_3 & 0xFFFF0000) + || (ErrorMark_L1_4 & 0xFFFF0000) ) + { + printf("Check DQ connections to/from U12 (front) and U24 (back)\n"); + } + } + else if(tmu == 1) + { + if( (ErrorMark_L1_1 & 0xFFFF) + || (ErrorMark_L1_2 & 0xFFFF) + || (ErrorMark_L1_3 & 0xFFFF) + || (ErrorMark_L1_4 & 0xFFFF) ) + { + printf("Check DQ connections to/from U13 (front) and U27 (back)\n"); + } + + if( (ErrorMark_L1_1 & 0xFFFF0000) + || (ErrorMark_L1_2 & 0xFFFF0000) + || (ErrorMark_L1_3 & 0xFFFF0000) + || (ErrorMark_L1_4 & 0xFFFF0000) ) + { + printf("Check DQ connections to/from U11 (front) and U28 (back)\n"); + } + } + + } + if(bErrHighBytes) + { + if(ucNumTMU == 0) + { + if( (ErrorMark_L2_1 & 0xFFFF) + || (ErrorMark_L2_2 & 0xFFFF) + || (ErrorMark_L2_3 & 0xFFFF) + || (ErrorMark_L2_4 & 0xFFFF) ) + { + printf("Check DQ connections to/from U18 (front) and U25 (back)\n"); + } + + if( (ErrorMark_L2_1 & 0xFFFF0000) + || (ErrorMark_L2_2 & 0xFFFF0000) + || (ErrorMark_L2_3 & 0xFFFF0000) + || (ErrorMark_L2_4 & 0xFFFF0000) ) + { + printf("Check DQ connections to/from U17 (front) and U26 (back)\n"); + } + } + else if(ucNumTMU == 1) + { + if( (ErrorMark_L2_1 & 0xFFFF) + || (ErrorMark_L2_2 & 0xFFFF) + || (ErrorMark_L2_3 & 0xFFFF) + || (ErrorMark_L2_4 & 0xFFFF) ) + { + printf("Check DQ connections to/from U16 (front) and U29 (back)\n"); + } + + if( (ErrorMark_L2_1 & 0xFFFF0000) + || (ErrorMark_L2_2 & 0xFFFF0000) + || (ErrorMark_L2_3 & 0xFFFF0000) + || (ErrorMark_L2_4 & 0xFFFF0000) ) + { + printf("Check DQ connections to/from U15 (front) and U32 (back)\n"); + } + } + + } + + }*/ + + /* reset the Init0 register back to its previous value */ + sst1InitIdle(sst); + ISET(SST_TREX(sst,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + return NbErr; +} + +unsigned long long +test_TMU_datalines( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const unsigned char ucNumTMU, + const unsigned char bRandom, + const unsigned char RamSizeMB) +{ + typedef struct _def_sMemBlock{ + unsigned long ulAddStart; + unsigned long ulAddEnd; + unsigned long ulAddLength; + }def_sMemBlock; + + const def_sMemBlock ar_memBlocks[] = { + { .ulAddStart = 0x000000, + .ulAddLength = 0x100000 + }, + { .ulAddStart = 0x100000, + .ulAddLength = 0x100000 + }, + { .ulAddStart = 0x200000, + .ulAddLength = 0x100000 + }, + { .ulAddStart = 0x300000, + .ulAddLength = 0x100000 + }, + }; + + unsigned long long ullNbErrorAll = 0; + + // set downstream TMUs to passthrough + for (int i=0; itextureMode, SST_TC_PASS | SST_TCA_PASS); + + for( int iMemBlock = 0; + iMemBlock <= sizeof(ar_memBlocks)/sizeof(def_sMemBlock); + iMemBlock++) + { + const def_sMemBlock* pMemBlk = &ar_memBlocks[iMemBlock]; + + if(RamSizeMB<4 && pMemBlk->ulAddStart >= 0x300000) continue; + if(RamSizeMB<3 && pMemBlk->ulAddStart >= 0x200000) continue; + if(RamSizeMB<2 && pMemBlk->ulAddStart >= 0x100000) continue; + /* + printf("Testing memory block 0x%08x to 0x%08x ...\n", + pMemBlk->ulAddStart, + pMemBlk->ulAddStart + pMemBlk->ulAddLength -4); + */ + unsigned char ucAddMovingBit = 0; + for( FxU32 addrTest = pMemBlk->ulAddStart ; + addrTest < (pMemBlk->ulAddStart + pMemBlk->ulAddLength); + ucAddMovingBit++) + { + FxU32 bitTest = 1u; + FxU32 bitTest2 = 1u<<31; + for(unsigned long nloop=0;; nloop++) + { + unsigned long ulNbError; + ulNbError = RenderTest( devInfo, + sst, + sstregs, + ucNumTMU, + addrTest, + bitTest, + bitTest2); + ullNbErrorAll += ulNbError; + + if((bRandom && (nloop > 32)) || bitTest == 0) + { + break; + } + bitTest = bRandom ? get_notnull_random_balanced_mByte() : (bitTest << 1); + bitTest2 = bRandom ? get_notnull_random_balanced_mByte() : (bitTest2 >> 1); + } + //printf("Done @ 0x%08x\n",dataTest); + + const FxU32 new_addrTest = pMemBlk->ulAddStart | (1 << ucAddMovingBit); + if(new_addrTest == pMemBlk->ulAddStart) break; + addrTest = new_addrTest; + } + } + + return ullNbErrorAll; +} diff --git a/Test_Data.h b/Test_Data.h new file mode 100644 index 0000000..1be9bbf --- /dev/null +++ b/Test_Data.h @@ -0,0 +1,12 @@ +#ifndef _DEF_TEST_DATA_H_ +#define _DEF_TEST_DATA_H_ + +unsigned long long +test_TMU_datalines( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const unsigned char ucNumTMU, + const unsigned char bRandom, + const unsigned char RamSizeMB); + +#endif //_DEF_TEST_DATA_H_ diff --git a/Test_Data_Huge.c b/Test_Data_Huge.c new file mode 100644 index 0000000..455c774 --- /dev/null +++ b/Test_Data_Huge.c @@ -0,0 +1,248 @@ +#include +#include +#include +#include + +#include +#include +#include +#include <3dfx.h> +#include + +#include "FaultSources.h" +#include "Utils.h" +#include "Draw.h" + +#include "Test_Data_Huge.h" + +static unsigned long long +RenderTest( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const char ucNumTMU, + const FxU32 mem) +{ + unsigned long NbErr = 0; + + clock_t begin = clock(); + + ISET(sstregs->texBaseAddr, (mem>>3)); /* set to mem addr */ + + #define _DEF_NB_PIXEL_ROW 256 + #define _DEF_NB_PIXEL_COL 256 + + static unsigned short + ar_u16Pixels[_DEF_NB_PIXEL_ROW][_DEF_NB_PIXEL_COL]; + static unsigned long + ar_u16PixelsRaw[_DEF_NB_PIXEL_ROW][_DEF_NB_PIXEL_COL/2]; + static unsigned short + ar_u16PixelsReRead[_DEF_NB_PIXEL_ROW][_DEF_NB_PIXEL_COL]; + + for(unsigned short iter_row = 0; iter_row < _DEF_NB_PIXEL_ROW; iter_row++) + { + for(unsigned short iter_col = 0; iter_col < _DEF_NB_PIXEL_COL; iter_col+=2) + { + const unsigned long NewData = get_notnull_random_balanced_mByte(); + ar_u16PixelsRaw[iter_row][iter_col/2] = NewData; + ar_u16Pixels[iter_row][iter_col] = NewData >>16; + ar_u16Pixels[iter_row][iter_col+1] = NewData & 0xFFFF; + } + } + clock_t after_create = clock(); + + + volatile FxU32 *texRowAddr + = (ucNumTMU<<(21-2)) + (((FxU32)0/*LOD0*/)<<(17-2)) + + (FxU32 *)SST_TEX_ADDRESS(sstregs); + + for(unsigned short iter_row = 0; iter_row < _DEF_NB_PIXEL_ROW; iter_row++) + { + for(unsigned short iter_col = 0; iter_col < _DEF_NB_PIXEL_COL/2; iter_col++) + { + //printf("writing %d\n",ar_u16PixelsRaw[iter_row][iter_col]); + ISET(texRowAddr[iter_col], ar_u16PixelsRaw[iter_row][iter_col]); + } + texRowAddr += (1<<(9-2)); //jump to next line + } + clock_t after_write = clock(); + #define NB_CHECK_LOOP 3 + clock_t before_draw[NB_CHECK_LOOP]; + clock_t after_draw[NB_CHECK_LOOP]; + clock_t after_read[NB_CHECK_LOOP]; + clock_t after_check[NB_CHECK_LOOP]; + for(unsigned int i = 0; i> 16; + ar_u16PixelsReRead[iter_row][iter_col+1] = *rptr & 0xFFFF; + rptr+=1; + } + rptr+=info.strideInBytes>>2; + } + grLfbUnlock(GR_LFB_READ_ONLY,GR_BUFFER_FRONTBUFFER); + } + else + { + printf("NOT LFB access.\n"); + } + */ + volatile FxU32* pLFB = sst + (SST_LFB_ADDR>>2); + for(unsigned short iter_row = 0; iter_row < _DEF_NB_PIXEL_ROW; iter_row++) + { + + //printf("reading row %d\n",iter_row); + for(unsigned short iter_col = 0; iter_col < _DEF_NB_PIXEL_COL; iter_col+=2) + { + const FxU32 u32Data = *pLFB++; + ar_u16PixelsReRead[iter_row][iter_col] = u32Data >> 16; + ar_u16PixelsReRead[iter_row][iter_col+1] = u32Data & 0xFFFF; + + //printf("read: %d\n",u32Data); + } + + pLFB += ((2048)>>2) - ((_DEF_NB_PIXEL_COL*2) >>2) ; + + } + after_read[i] = clock(); + + for(unsigned short iter_row = 0; iter_row < _DEF_NB_PIXEL_ROW; iter_row++) + { + //printf("checking row %d\n",iter_row); + for(unsigned short iter_col = 0; iter_col < _DEF_NB_PIXEL_COL; iter_col+=2) + { + if(ar_u16PixelsReRead[iter_row][iter_col] != ar_u16Pixels[iter_row][iter_col]) + {/* + printf("Error pix1 on row %d, col %d: expected %04x, got %04x\n", + iter_row, iter_col, + ar_u16Pixels[iter_row][iter_col], + ar_u16PixelsReRead[iter_row][iter_col]);*/ + NbErr++; + } + if(ar_u16PixelsReRead[iter_row][iter_col+1] != ar_u16Pixels[iter_row][iter_col+1]) + {/* + printf("Error pix2 on row %d, col %d: expected %04x, got %04x\n", + iter_row, iter_col, + ar_u16Pixels[iter_row][iter_col+1], + ar_u16PixelsReRead[iter_row][iter_col+1]);*/ + NbErr++; + } + } + } + after_check[i] = clock(); + } + /* + clock_t end = clock(); + printf("time to create: %f\n",(double)(after_create-begin)/CLOCKS_PER_SEC); + printf("time to write: %f\n",(double)(after_write-after_create)/CLOCKS_PER_SEC); + for(unsigned int i = 0; itmuInit0[tmu] = SST_TREXINIT0_DEFAULT | BIT(20); // BIT(20) seems to use bank 2...even if TMU mem is <= 2MB + + devInfo->tmuInit0[(int)ucNumTMU] = SST_TREXINIT0_DEFAULT ; + + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + /* + sst1InitIdle(sst); + ISET(SST_TREX(sstregs,ucNumTMU)->trexInit0, 0x5000 | (devInfo->tmuInit0[(int)ucNumTMU] & ~0x7000)); + sst1InitIdle(sst); + */ + + // set downstream TMUs to passthrough + for (int i=0; itextureMode, SST_TC_PASS | SST_TCA_PASS); + + for( int iMemBlock = 0; + iMemBlock <= sizeof(ar_memBlocks)/sizeof(def_sMemBlock); + iMemBlock++) + { + const def_sMemBlock* pMemBlk = &ar_memBlocks[iMemBlock]; + if(RamSizeMB<4 && pMemBlk->ulAddStart >= 0x300000) continue; + if(RamSizeMB<3 && pMemBlk->ulAddStart >= 0x200000) continue; + if(RamSizeMB<2 && pMemBlk->ulAddStart >= 0x100000) continue; + //printf("RamSizeMB= %d, ulAddStart=%08x\n", RamSizeMB,pMemBlk->ulAddStart); + + for( FxU32 addrTest = pMemBlk->ulAddStart ; + addrTest < (pMemBlk->ulAddStart + pMemBlk->ulAddLength); + addrTest += 65536) //256x256x2 (16bit pixels texture) + { + //printf("Testing memory block 0x%08x ...\n", addrTest); + ullNbErrorAll += RenderTest( devInfo, + sst, + sstregs, + ucNumTMU, + addrTest); + } + } + + /* reset the Init0 register back to its previous value */ + sst1InitIdle(sst); + ISET(SST_TREX(sst,ucNumTMU)->trexInit0, devInfo->tmuInit0[(int)ucNumTMU]); + sst1InitIdle(sst); + + return ullNbErrorAll; +} diff --git a/Test_Data_Huge.h b/Test_Data_Huge.h new file mode 100644 index 0000000..e278026 --- /dev/null +++ b/Test_Data_Huge.h @@ -0,0 +1,11 @@ +#ifndef _DEF_TEST_DATA_HUGE_H_ +#define _DEF_TEST_DATA_HUGE_H_ + +unsigned long long +test_TMU_datalines_Huge( sst1DeviceInfoStruct* devInfo, + FxU32* sst, + SstRegs *sstregs, + const unsigned char ucNumTMU, + const unsigned char RamSizeMB); + +#endif //_DEF_TEST_DATA_HUGE_H_ diff --git a/Utils.c b/Utils.c new file mode 100644 index 0000000..174bea8 --- /dev/null +++ b/Utils.c @@ -0,0 +1,102 @@ +#define _BSD_SOURCE 1 +#include +#include + +#include "Utils.h" + +inline void +printbin32( const unsigned long ulVal, + const unsigned char bGroupByBytes) +{ + for(unsigned long idxBit = 1<<31;idxBit>0;idxBit>>=1) + { + if(bGroupByBytes) + switch(idxBit) + { + case 1<<23: + case 1<<15: + case 1<<7: + putchar(' '); + } + putchar(ulVal & idxBit ? '1' : '0'); + } +} + +inline unsigned char +count_bit32(const unsigned long ulVal) +{ + unsigned char cpt = 0; + for(unsigned long idxBit = 1<<31;idxBit>0;idxBit>>=1) + if(ulVal & idxBit) + cpt++; + return cpt; +} + +inline unsigned char +count_bit8(const unsigned char ulVal) +{ + unsigned char cpt = 0; + for(unsigned char idxBit = 1<<7;idxBit>0;idxBit>>=1) + if(ulVal & idxBit) + cpt++; + return cpt; +} + +inline void +printbin32Info( const unsigned long ulVal, + const unsigned short uhb, + const unsigned short ulb) +{ + printbin32(ulVal,1); + putchar('\n'); + printf("%02d....%02d %02d....%02d %02d....%02d %02d....%02d\n", + uhb, + 3*(uhb+ulb+1)/4, 3*((uhb+ulb+1)/4)-1, + (uhb+ulb+1)/2, ((uhb+ulb+1)/2)-1, + (uhb+ulb+1)/4, ((uhb+ulb+1)/4)-1, + ulb); +} + +unsigned long get_notnull_random() +{ + unsigned long val; + do + val = random()<<1 ^ random(); + while(!val); + return val; +} + +unsigned long get_notnull_random_balanced() +{ + unsigned long val; + do + val = random()<<1 ^ random(); + while(count_bit32(val) != 16); + return val; +} + + +unsigned char get_notnull8_random_balanced() +{ + unsigned char val; + static unsigned char prev = 0; + do + val = random()<<1 ^ random(); + while((count_bit8(val) != 4) || (val == prev)); + prev = val; + return val; +} + +unsigned long get_notnull_random_balanced_mByte() +{ + unsigned long val; + static unsigned long prev = 0; + do + val = (get_notnull8_random_balanced() << 24) + | (get_notnull8_random_balanced() << 16) + | (get_notnull8_random_balanced() << 8) + | (get_notnull8_random_balanced() << 0); + while(val == prev); + prev = val; + return val; +} diff --git a/Utils.h b/Utils.h new file mode 100644 index 0000000..25e5bec --- /dev/null +++ b/Utils.h @@ -0,0 +1,13 @@ +#ifndef _DEF_UTILS_H_ +#define _DEF_UTILS_H_ + +inline void printbin32(const unsigned long ulVal,const unsigned char bGroupByBytes); +inline unsigned char count_bit32(const unsigned long ulVal); +inline unsigned char count_bit8(const unsigned char ulVal); +inline void printbin32Info(const unsigned long ulVal, const unsigned short uhb, const unsigned short ulb); +unsigned long get_notnull_random(); +unsigned long get_notnull_random_balanced(); +unsigned char get_notnull8_random_balanced(); +unsigned long get_notnull_random_balanced_mByte(); + +#endif //_DEF_UTILS_H_ diff --git a/main.c b/main.c new file mode 100644 index 0000000..ee17d97 --- /dev/null +++ b/main.c @@ -0,0 +1,157 @@ +#define _BSD_SOURCE 1 +#include +#include +#include +#include +#include + +#include +#include +#include +#include <3dfx.h> +#include + +#include "FaultSources.h" +#include "Utils.h" +#include "Draw.h" + +#include "Test_Address.h" +#include "Test_Data.h" +#include "Test_Data_Huge.h" + +int main(int argc, char **argv) +{ + unsigned long long ullNbErrorAll = 0; + const FxU32 boardNum = 0; + //const int TMU_to_test = 0; + //const unsigned char bRandom = 1; + + sst1DeviceInfoStruct devInfo; + FxU32* sst; + SstRegs *sstregs; + + printf("3Dfx Voodoo2 TMU memory tester v1.0\n(c) ChaCha, 2026\n\n"); + + srandom(time(NULL)); + FaultSource_Reset(); + + for(int j=0; j<100; j++) + { + + if ((sst = sst1InitMapBoard(boardNum)) == NULL) + { + fprintf(stderr, "No Voodoo boards found\n"); + exit(-1); + } + + sst1InitRegisters(sst); + + if (sst1InitGetDeviceInfo(sst, &devInfo) == FXFALSE) + { + fprintf(stderr, "Couldn't get info for Voodoo # %d\n", boardNum); + exit(-1); + } + /* + grGlideInit(); + GrHwConfiguration hwconfig; + if(!grSstQueryHardware(&hwconfig)) + { + fprintf(stderr, "Couldn't get glide info for Voodoo # %d\n", boardNum); + exit(-1); + } + grSstSelect(boardNum); + */ + sstregs = (SstRegs *) sst; + + printf("FBI Memory: %d MB\n", devInfo.fbiMemSize); + for (int tmu = 0; tmu < devInfo.numberTmus; tmu++) + { + printf("TMU %d RAM: %d MB\n", tmu, devInfo.tmuMemSize[tmu]); + } + putchar('\n'); + + ISET(sstregs->lfbMode, SST_LFB_RGBALANES_ARGB | SST_LFB_READFRONTBUFFER); + ISET(sstregs->fbzMode, SST_DRAWBUFFER_FRONT | SST_RGBWRMASK); + ISET(sstregs->fbzColorPath, SST_RGBSEL_TREXOUT | SST_CC_PASS | SST_ENTEXTUREMAP); + ISET(sstregs->textureMode, SST_RGB565 | SST_TC_REPLACE | SST_TCA_REPLACE); + ISET(sstregs->tLOD, 0); + + //if(devInfo.tmuMemSize[1]==1) continue; + //devInfo.numberTmus=1; + //devInfo.tmuMemSize[1]==1; + for (int tmu = 0; tmu < devInfo.numberTmus; tmu++) + { + printf("Testing Board %d, TMU %d, %dMB \n\n",boardNum,tmu,devInfo.tmuMemSize[tmu]); + + puts("# address & control lines test - cumulated"); + for(int j=0;j<100;j++) + { + const unsigned long long err + = RenderTestAddress(&devInfo, + sst, + sstregs, + tmu, + devInfo.tmuMemSize[tmu]); + ullNbErrorAll += err; + putchar( err ? 'E' : '-'); + fflush(stdout); + } + putchar('\n'); + + puts("# data test - single bit move"); + for(int j=0;j<100;j++) + { + const unsigned long long err + = test_TMU_datalines(&devInfo, + sst, + sstregs, + tmu , + 0, //bit shift + devInfo.tmuMemSize[tmu]); + ullNbErrorAll += err; + putchar( err ? 'E' : '-'); + fflush(stdout); + } + putchar('\n'); + + puts("# data test - random pattern"); + for(int j=0;j<100;j++) + { + const unsigned long long err + = test_TMU_datalines(&devInfo, + sst, + sstregs, + tmu , + 1, // random + devInfo.tmuMemSize[tmu]); + ullNbErrorAll += err; + putchar( err ? 'E' : '-'); + fflush(stdout); + } + putchar('\n'); + + puts("# data test - huge data"); + for(int j=0;j<10;j++) + { + const unsigned long long err + = test_TMU_datalines_Huge( &devInfo, + sst, + sstregs, + tmu , + devInfo.tmuMemSize[tmu]); + ullNbErrorAll += err; + putchar( err ? 'E' : '-'); + fflush(stdout); + } + putchar('\n'); + } + } + + FaultSource_Sort(); + FaultSource_Display(); + + printf("Test Complete, ullNbErrorAll = %lld\n",ullNbErrorAll); + //grGlideShutdown(); + pciClose(); + return 0; +}