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implement no-mem test and start validating / tuning with real hardware

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ChaCha
2026-03-15 22:18:42 +01:00
parent 3ba8a3a985
commit c363aa6284
22 changed files with 2780 additions and 546 deletions
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503
Test_Address.c
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@@ -14,13 +14,17 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#include <stdint.h>
#include <stdio.h>
#include "cvg.h"
#include <glide.h>
#include "sst1init.h"
#include "fxpci.h"
#include "Utils.h"
#include "V2MemTest.h"
#include "FaultSources.h"
#include "Utils.h"
#include "Draw.h"
@@ -35,9 +39,9 @@ typedef struct _def_sTestAddress {
}def_sTestAddress;
unsigned long
RenderTestAddress( sst1DeviceInfoStruct* devInfo,
FxU32* sst,
SstRegs *sstregs,
RenderTestAddress( sst1DeviceInfoStruct * const devInfo,
FxU32 * const sst,
SstRegs * const sstregs,
const char ucNumTMU,
const unsigned char RamSizeMB,
def_sFaultSourceScoreRec* const pFaultSrcCtx)
@@ -64,24 +68,24 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
{0x000004,0,0,0,0}
*/
{0x000008,0,1,0},
/* {target pin}, { + previous adjacent pin} */
{0x000010,0,2,0}, {0x000018,0,2,0},
{0x000020,0,3,0}, {0x000030,0,3,0},
{0x000040,0,4,0}, {0x000060,0,4,0},
{0x000080,0,5,0}, {0x0000C0,0,5,0},
{0x000100,0,6,0}, {0x000180,0,6,0},
{0x000200,0,7,0}, {0x000300,0,7,0},
{0x000400,0,8,0}, {0x000600,0,8,0},
{0x000800,0,9,0}, {0x000C00,0,9,0},
{0x001000,0,0,1}, {0x001800,0,0,1},
{0x002000,0,0,2}, {0x003000,0,0,2},
{0x004000,0,0,3}, {0x006000,0,0,3},
{0x008000,0,0,4}, {0x00C000,0,0,4},
{0x010000,0,0,5}, {0x018000,0,0,5},
{0x020000,0,0,6}, {0x030000,0,0,6},
{0x040000,0,0,7}, {0x060000,0,0,7},
{0x080000,0,0,8}, {0x0C0000,0,0,8},
{0x100000,0,0,9}, {0x180000,0,0,9},
/* {target pin} */
{0x000010,0,2,0},
{0x000020,0,3,0},
{0x000040,0,4,0},
{0x000080,0,5,0},
{0x000100,0,6,0},
{0x000200,0,7,0},
{0x000400,0,8,0},
{0x000800,0,9,0},
{0x001000,0,0,1},
{0x002000,0,0,2},
{0x004000,0,0,3},
{0x008000,0,0,4},
{0x010000,0,0,5},
{0x020000,0,0,6},
{0x040000,0,0,7},
{0x080000,0,0,8},
{0x100000,0,0,9},
/* Bank1 */
{0x200000,1,0,0},
@@ -91,26 +95,27 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
{0x200004,1,0,0,0}
*/
{0x200008,1,1,0},
/* {target pin}, { + previous adjacent pin} */
{0x200010,1,2,0}, {0x200018,1,2,0},
{0x200020,1,3,0}, {0x200030,1,3,0},
{0x200040,1,4,0}, {0x200060,1,4,0},
{0x200080,1,5,0}, {0x2000C0,1,5,0},
{0x200100,1,6,0}, {0x200180,1,6,0},
{0x200200,1,7,0}, {0x200300,1,7,0},
{0x200400,1,8,0}, {0x200600,1,8,0},
{0x200800,1,9,0}, {0x200C00,1,9,0},
{0x201000,1,0,1}, {0x201800,1,0,1},
{0x202000,1,0,2}, {0x203000,1,0,2},
{0x204000,1,0,3}, {0x206000,1,0,3},
{0x208000,1,0,4}, {0x20C000,1,0,4},
{0x210000,1,0,5}, {0x218000,1,0,5},
{0x220000,1,0,6}, {0x230000,1,0,6},
{0x240000,1,0,7}, {0x260000,1,0,7},
{0x280000,1,0,8}, {0x2C0000,1,0,8},
{0x300000,1,0,9}, {0x380000,1,0,9},
/* {target pin} */
{0x200010,1,2,0},
{0x200020,1,3,0},
{0x200040,1,4,0},
{0x200080,1,5,0},
{0x200100,1,6,0},
{0x200200,1,7,0},
{0x200400,1,8,0},
{0x200800,1,9,0},
{0x201000,1,0,1},
{0x202000,1,0,2},
{0x204000,1,0,3},
{0x208000,1,0,4},
{0x210000,1,0,5},
{0x220000,1,0,6},
{0x240000,1,0,7},
{0x280000,1,0,8},
{0x300000,1,0,9},
};
logD("testing %d MB of memory\n",RamSizeMB);
for(unsigned char idx=0;
idx < (sizeof(add_list)/sizeof(def_sTestAddress));
idx++)
@@ -120,10 +125,40 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
if(RamSizeMB<3 && add_list[idx].u32Addr >= 0x200000) continue;
if(RamSizeMB<2 && add_list[idx].u32Addr >= 0x100000) continue;
logT("idx = %d\n",idx);
logT("u32Addr = 0x%08X\n",add_list[idx].u32Addr);
const uint32_t TestVal1 = get_notnull_random_balanced_mByte();
const uint32_t TestVal2 = get_notnull_random_balanced_mByte();
const uint32_t TestValBlank1 = get_notnull_random_balanced_mByte();
const uint32_t TestValBlank2 = get_notnull_random_balanced_mByte();
logT("TestVal1 = %08X\n",TestVal1);
uint32_t TestVal2 = 0;
do
{
TestVal2 = get_notnull_random_balanced_mByte();
}
while((count_bit32((TestVal2 ^ TestVal1)) < 12));
logT("TestVal2 = %08X\n",TestVal2);
uint32_t TestValBlank1 = 0;
do
{
TestValBlank1 = get_notnull_random_balanced_mByte();
}
while( (count_bit32((TestValBlank1 ^ TestVal1) & 0x0000FFFF) < 6)
|| (count_bit32((TestValBlank1 ^ TestVal1) & 0xFFFF0000) < 6)
|| (count_bit32((TestValBlank1 ^ TestVal2)) < 12));
logT("TestValBlank1 = %08X\n",TestValBlank1);
uint32_t TestValBlank2 = 0;
do
{
TestValBlank2 = get_notnull_random_balanced_mByte();
}
while( (count_bit32((TestValBlank2 ^ TestVal2) & 0x0000FFFF) < 6)
|| (count_bit32((TestValBlank2 ^ TestVal2) & 0xFFFF0000) < 6)
|| (count_bit32((TestValBlank2 ^ TestValBlank1)) < 12)
|| (count_bit32((TestValBlank2 ^ TestVal1)) < 12));
logT("TestValBlank2 = %08X\n",TestValBlank2);
/* Clearing memory targets */
for(unsigned char idxclr=0;
@@ -136,7 +171,7 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
if(RamSizeMB<2 && add_list[idxclr].u32Addr >= 0x100000) continue;
/* set base mem @ */
ISET(sstregs->texBaseAddr, (add_list[idxclr].u32Addr>>3));
ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (add_list[idxclr].u32Addr>>3));
/* set @ to first line, using bits 00..31*/
volatile const FxU32 *texAddrBlank
@@ -157,7 +192,7 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
}
/* set base mem @ */
ISET(sstregs->texBaseAddr, (add_list[idx].u32Addr>>3));
ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (add_list[idx].u32Addr>>3));
/* set @ to first line, using bits 00..31*/
volatile const FxU32 *texAddr
@@ -184,18 +219,18 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
if(RamSizeMB<4 && add_list[idxdraw].u32Addr >= 0x300000) continue;
if(RamSizeMB<3 && add_list[idxdraw].u32Addr >= 0x200000) continue;
if(RamSizeMB<2 && add_list[idxdraw].u32Addr >= 0x100000) continue;
logT("idxdraw = %d, row = %d; col = %d\n",idxdraw,add_list[idxdraw].nRowBit,add_list[idxdraw].nColBit);
/* testing copy beyond tested bit is useless & can raise
false positive */
if(idxdraw > idx) break;
//if(idxdraw > idx) break;
clearScreen(sstregs,0x00000000,2,2);
/* set to mem addr */
ISET(sstregs->texBaseAddr, (add_list[idxdraw].u32Addr >> 3));
ISET(SST_TREX(sstregs,ucNumTMU)->texBaseAddr, (add_list[idxdraw].u32Addr >> 3));
/* draw a 2x2 square */
drawSquare(sstregs, 0, 0, 2);
drawSquare(sstregs, ucNumTMU, 0, 0, 2);
sst1InitIdle(sst);
/* first line, to use bits 00..31 */
@@ -206,93 +241,33 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
const uint32_t ErrorMark_L1 = (idxdraw == idx) ? (L1 ^ TestVal1) : (L1 ^ TestValBlank1);
const uint32_t ErrorMark_L2 = (idxdraw == idx) ? (L2 ^ TestVal2) : (L2 ^ TestValBlank2);
const uint32_t ErrorMarkBlank_L1 = (idxdraw == idx) ? (L1 ^ TestValBlank1) : (L1 ^ TestVal1);
const uint32_t ErrorMarkBlank_L2 = (idxdraw == idx) ? (L2 ^ TestValBlank2) : (L2 ^ TestVal2) ;
const uint32_t ErrorMarkOther_L1 = (idxdraw == idx) ? (L1 ^ TestValBlank1) : (L1 ^ TestVal1);
const uint32_t ErrorMarkOther_L2 = (idxdraw == idx) ? (L2 ^ TestValBlank2) : (L2 ^ TestVal2);
if(ErrorMark_L1 || ErrorMark_L2)
{
const def_eFaultSource TMUTexADDR_0_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_0_0 : U8_TMU1_TEX_ADDR_0_0;
const def_eFaultSource TMUTexADDR_1_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_1_0 : U8_TMU1_TEX_ADDR_1_0;
const def_eFaultSource TMUTexADDR_2_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_2_0 : U8_TMU1_TEX_ADDR_2_0;
const def_eFaultSource TMUTexADDR_3_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_3_0 : U8_TMU1_TEX_ADDR_3_0;
const def_eFaultSource TMUTexWE = (ucNumTMU == 0) ? U9_TMU0_TEX_WE : U8_TMU1_TEX_WE;
const def_eFaultSource TMUTexCAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS0 : U8_TMU1_TEX_CAS0;
const def_eFaultSource TMUTexCAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS1 : U8_TMU1_TEX_CAS1;
const def_eFaultSource TMUTexCAS2 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS2 : U8_TMU1_TEX_CAS2;
const def_eFaultSource TMUTexCAS3 = (ucNumTMU == 0) ? U9_TMU0_TEX_CAS3 : U8_TMU1_TEX_CAS3;
const def_eFaultSource _TMUTexRAS0 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS0 : U8_TMU1_TEX_RAS0;
const def_eFaultSource _TMUTexRAS1 = (ucNumTMU == 0) ? U9_TMU0_TEX_RAS1 : U8_TMU1_TEX_RAS1;
const def_eFaultSource TMUTexRASCurrent = (add_list[idxdraw].nBank == 0) ? _TMUTexRAS0 : _TMUTexRAS1;
const def_eFaultSource _MEMChip_B0_0_A0 = (ucNumTMU == 0) ? U14_A0 : U13_A0;
const def_eFaultSource _MEMChip_B0_1_A0 = (ucNumTMU == 0) ? U12_A0 : U11_A0;
const def_eFaultSource _MEMChip_B0_2_A0 = (ucNumTMU == 0) ? U18_A0 : U16_A0;
const def_eFaultSource _MEMChip_B0_3_A0 = (ucNumTMU == 0) ? U17_A0 : U15_A0;
const def_eFaultSource _MEMChip_B1_0_A0 = (ucNumTMU == 0) ? U23_A0 : U27_A0;
const def_eFaultSource _MEMChip_B1_1_A0 = (ucNumTMU == 0) ? U24_A0 : U28_A0;
const def_eFaultSource _MEMChip_B1_2_A0 = (ucNumTMU == 0) ? U25_A0 : U29_A0;
const def_eFaultSource _MEMChip_B1_3_A0 = (ucNumTMU == 0) ? U26_A0 : U30_A0;
const def_eFaultSource TMUTexADDR_0_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_0_0 : U8_TMU1_TEX_ADDR_0_0;
const def_eFaultSource TMUTexADDR_1_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_1_0 : U8_TMU1_TEX_ADDR_1_0;
const def_eFaultSource TMUTexADDR_2_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_2_0 : U8_TMU1_TEX_ADDR_2_0;
const def_eFaultSource TMUTexADDR_3_0 = (ucNumTMU == 0) ? U9_TMU0_TEX_ADDR_3_0 : U8_TMU1_TEX_ADDR_3_0;
const def_eFaultSource _MEMChip_B0_0_A0 = (ucNumTMU == 0) ? U14_A0 : U13_A0;
const def_eFaultSource _MEMChip_B0_1_A0 = (ucNumTMU == 0) ? U12_A0 : U11_A0;
const def_eFaultSource _MEMChip_B0_2_A0 = (ucNumTMU == 0) ? U18_A0 : U16_A0;
const def_eFaultSource _MEMChip_B0_3_A0 = (ucNumTMU == 0) ? U17_A0 : U15_A0;
const def_eFaultSource _MEMChip_B1_0_A0 = (ucNumTMU == 0) ? U23_A0 : U27_A0;
const def_eFaultSource _MEMChip_B1_1_A0 = (ucNumTMU == 0) ? U24_A0 : U28_A0;
const def_eFaultSource _MEMChip_B1_2_A0 = (ucNumTMU == 0) ? U25_A0 : U29_A0;
const def_eFaultSource _MEMChip_B1_3_A0 = (ucNumTMU == 0) ? U26_A0 : U30_A0;
const def_eFaultSource MEMChip_0_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_A0 : _MEMChip_B1_0_A0;
const def_eFaultSource MEMChip_1_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_A0 : _MEMChip_B1_1_A0;
const def_eFaultSource MEMChip_2_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_A0 : _MEMChip_B1_2_A0;
const def_eFaultSource MEMChip_3_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_A0 : _MEMChip_B1_3_A0;
const def_eFaultSource MEMChip_1_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_A0 : _MEMChip_B1_1_A0;
const def_eFaultSource MEMChip_2_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_A0 : _MEMChip_B1_2_A0;
const def_eFaultSource MEMChip_3_A0 = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_A0 : _MEMChip_B1_3_A0;
const def_eFaultSource _MEMChip_B0_0_CASL = (ucNumTMU == 0) ? U14_CASL : U13_CASL;
const def_eFaultSource _MEMChip_B0_1_CASL = (ucNumTMU == 0) ? U12_CASL : U11_CASL;
const def_eFaultSource _MEMChip_B0_2_CASL = (ucNumTMU == 0) ? U18_CASL : U16_CASL;
const def_eFaultSource _MEMChip_B0_3_CASL = (ucNumTMU == 0) ? U17_CASL : U15_CASL;
const def_eFaultSource _MEMChip_B1_0_CASL = (ucNumTMU == 0) ? U23_CASL : U27_CASL;
const def_eFaultSource _MEMChip_B1_1_CASL = (ucNumTMU == 0) ? U24_CASL : U28_CASL;
const def_eFaultSource _MEMChip_B1_2_CASL = (ucNumTMU == 0) ? U25_CASL : U29_CASL;
const def_eFaultSource _MEMChip_B1_3_CASL = (ucNumTMU == 0) ? U26_CASL : U30_CASL;
const def_eFaultSource MEMChip_0_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_CASL : _MEMChip_B1_0_CASL;
const def_eFaultSource MEMChip_1_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_CASL : _MEMChip_B1_1_CASL;
const def_eFaultSource MEMChip_2_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_CASL : _MEMChip_B1_2_CASL;
const def_eFaultSource MEMChip_3_CASL = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_CASL : _MEMChip_B1_3_CASL;
const def_eFaultSource _MEMChip_B0_0_CASH = (ucNumTMU == 0) ? U14_CASH : U13_CASH;
const def_eFaultSource _MEMChip_B0_1_CASH = (ucNumTMU == 0) ? U12_CASH : U11_CASH;
const def_eFaultSource _MEMChip_B0_2_CASH = (ucNumTMU == 0) ? U18_CASH : U16_CASH;
const def_eFaultSource _MEMChip_B0_3_CASH = (ucNumTMU == 0) ? U17_CASH : U15_CASH;
const def_eFaultSource _MEMChip_B1_0_CASH = (ucNumTMU == 0) ? U23_CASH : U27_CASH;
const def_eFaultSource _MEMChip_B1_1_CASH = (ucNumTMU == 0) ? U24_CASH : U28_CASH;
const def_eFaultSource _MEMChip_B1_2_CASH = (ucNumTMU == 0) ? U25_CASH : U29_CASH;
const def_eFaultSource _MEMChip_B1_3_CASH = (ucNumTMU == 0) ? U26_CASH : U30_CASH;
const def_eFaultSource MEMChip_0_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_CASH : _MEMChip_B1_0_CASH;
const def_eFaultSource MEMChip_1_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_CASH : _MEMChip_B1_1_CASH;
const def_eFaultSource MEMChip_2_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_CASH : _MEMChip_B1_2_CASH;
const def_eFaultSource MEMChip_3_CASH = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_CASH : _MEMChip_B1_3_CASH;
const def_eFaultSource _MEMChip_B0_0_RAS = (ucNumTMU == 0) ? U14_RAS : U13_RAS;
const def_eFaultSource _MEMChip_B0_1_RAS = (ucNumTMU == 0) ? U12_RAS : U11_RAS;
const def_eFaultSource _MEMChip_B0_2_RAS = (ucNumTMU == 0) ? U18_RAS : U16_RAS;
const def_eFaultSource _MEMChip_B0_3_RAS = (ucNumTMU == 0) ? U17_RAS : U15_RAS;
const def_eFaultSource _MEMChip_B1_0_RAS = (ucNumTMU == 0) ? U23_RAS : U27_RAS;
const def_eFaultSource _MEMChip_B1_1_RAS = (ucNumTMU == 0) ? U24_RAS : U28_RAS;
const def_eFaultSource _MEMChip_B1_2_RAS = (ucNumTMU == 0) ? U25_RAS : U29_RAS;
const def_eFaultSource _MEMChip_B1_3_RAS = (ucNumTMU == 0) ? U26_RAS : U30_RAS;
const def_eFaultSource MEMChip_0_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_RAS : _MEMChip_B1_0_RAS;
const def_eFaultSource MEMChip_1_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_RAS : _MEMChip_B1_1_RAS;
const def_eFaultSource MEMChip_2_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_RAS : _MEMChip_B1_2_RAS;
const def_eFaultSource MEMChip_3_RAS = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_RAS : _MEMChip_B1_3_RAS;
const def_eFaultSource _MEMChip_B0_0_WE = (ucNumTMU == 0) ? U14_WE : U13_WE;
const def_eFaultSource _MEMChip_B0_1_WE = (ucNumTMU == 0) ? U12_WE : U11_WE;
const def_eFaultSource _MEMChip_B0_2_WE = (ucNumTMU == 0) ? U18_WE : U16_WE;
const def_eFaultSource _MEMChip_B0_3_WE = (ucNumTMU == 0) ? U17_WE : U15_WE;
const def_eFaultSource _MEMChip_B1_0_WE = (ucNumTMU == 0) ? U23_WE : U27_WE;
const def_eFaultSource _MEMChip_B1_1_WE = (ucNumTMU == 0) ? U24_WE : U28_WE;
const def_eFaultSource _MEMChip_B1_2_WE = (ucNumTMU == 0) ? U25_WE : U29_WE;
const def_eFaultSource _MEMChip_B1_3_WE = (ucNumTMU == 0) ? U26_WE : U30_WE;
const def_eFaultSource MEMChip_0_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_0_WE : _MEMChip_B1_0_WE;
const def_eFaultSource MEMChip_1_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_1_WE : _MEMChip_B1_1_WE;
const def_eFaultSource MEMChip_2_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_2_WE : _MEMChip_B1_2_WE;
const def_eFaultSource MEMChip_3_WE = (add_list[idxdraw].nBank == 0) ? _MEMChip_B0_3_WE : _MEMChip_B1_3_WE;
const def_eFaultSource _RES_RAS0 = (ucNumTMU == 0) ? R118 : R115;
const def_eFaultSource _RES_RAS1 = (ucNumTMU == 0) ? R149 : R150;
const def_eFaultSource RES_RAS = (add_list[idxdraw].nBank == 0) ? _RES_RAS0 : _RES_RAS1;
const def_eFaultSource RES_CAS = (ucNumTMU == 0) ? RA36 : RA32;
const def_eFaultSource RES_WE = (ucNumTMU == 0) ? R117 : R114;
const def_eFaultSource MEMChip_0_A0_Other = (add_list[idxdraw].nBank == 1) ? _MEMChip_B0_0_A0 : _MEMChip_B1_0_A0;
const def_eFaultSource MEMChip_1_A0_Other = (add_list[idxdraw].nBank == 1) ? _MEMChip_B0_1_A0 : _MEMChip_B1_1_A0;
const def_eFaultSource MEMChip_2_A0_Other = (add_list[idxdraw].nBank == 1) ? _MEMChip_B0_2_A0 : _MEMChip_B1_2_A0;
const def_eFaultSource MEMChip_3_A0_Other = (add_list[idxdraw].nBank == 1) ? _MEMChip_B0_3_A0 : _MEMChip_B1_3_A0;
const def_eFaultSource RES_TEXADDR_0_L = (ucNumTMU == 0) ? RA35 : RA31;
const def_eFaultSource RES_TEXADDR_0_H = (ucNumTMU == 0) ? RA34 : RA30;
@@ -306,240 +281,166 @@ RenderTestAddress( sst1DeviceInfoStruct* devInfo,
const def_eFaultSource RES_TEXADDR_3_L = (ucNumTMU == 0) ? RA22 : RA20;
const def_eFaultSource RES_TEXADDR_3_H = (ucNumTMU == 0) ? RA21 : RA19;
const def_eFaultSource RES_TEXADDR_3_8 = (ucNumTMU == 0) ? R98 : R97;
if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 2)
{
NbErr++;
if((idxdraw == idx) && count_bit32(ErrorMark_L1 & 0x0000FFFF) > 6)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_WE, 1.0/1);
}
if(count_bit32(ErrorMarkBlank_L1 & 0x0000FFFF) < 3)
{
if(add_list[idx].nColBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_0_0 + add_list[idx].nColBit, 1.0/1);
if(add_list[idx].nColBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_L + add_list[idx].nColBit + 1, 1.0/2);
else if(add_list[idx].nColBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_H + add_list[idx].nColBit + 1, 1.0/2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_8 + 1, 1.0/2);
}
if(add_list[idx].nRowBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_0_0 + add_list[idx].nRowBit, 1.0/1);
if(add_list[idx].nRowBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_L + add_list[idx].nRowBit + 1, 1.0/2);
else if(add_list[idx].nRowBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_H + add_list[idx].nRowBit + 1, 1.0/2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_8 + 1, 1.0/2);
}
}
else
{
FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_RAS, 1.0/4);
if(ErrorMark_L1 & 0x000000FF)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS0, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+1, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_CASL, 1.0/8);
}
if(ErrorMark_L1 & 0x0000FF00)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS1, 1.0/16);;
FaultSource_addScore(pFaultSrcCtx, RES_CAS+2, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_CASH, 1.0/8);
}
}
}
/* considering error only if more than 6 over 16 bits
/* This test is simpler than I wanteed it to be. It focuses
* only on address lines. I thought that reading a totally
* unknown value can mean we have a control line issue but it
* is more complex. In case of 2 addresses lines shorted,
* the value we will get wont necessary be the one we wrote,
* at any place. I am not 100% sure why, but it might be
* because of EDO Ram Page mode... Or maybe lines are also used
* internally by the TMU.. or maybe I just missed something !
*
* Anyway, this test should do the job for @ lines (including
* shorted). And the Control lines will be tested in a different
* Module where @ lines wont change.
*/
/* Considering error only if more than 3 over 16 bits
* are wrong, because we are only testing addresses
* lines here */
if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 2)
if(count_bit32(ErrorMark_L1 & 0x0000FFFF) > 3)
{
NbErr++;
if((idxdraw == idx) && count_bit32(ErrorMark_L1 & 0xFFFF0000) > 6)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_WE, 1.0/1);
}
if(count_bit32(ErrorMarkBlank_L1 & 0xFFFF0000) < 3)
/* If it matches the Other value with less than
* 3 error bits */
if(count_bit32(ErrorMarkOther_L1 & 0x0000FFFF) < 3)
{
if(add_list[idx].nColBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_1_0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0 + add_list[idx].nColBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0_Other + add_list[idx].nColBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_0_0 + add_list[idx].nColBit - 1, 1.0 / 2);
if(add_list[idx].nColBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_L + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_L + add_list[idx].nColBit - 2, 1.0 / 2);
else if(add_list[idx].nColBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_H + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_H + add_list[idx].nColBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_8 + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_8, 1.0 / 2);
}
if(add_list[idx].nRowBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_1_0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0 + add_list[idx].nRowBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_0_A0_Other + add_list[idx].nRowBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_0_0 + add_list[idx].nRowBit - 1, 1.0 / 2);
if(add_list[idx].nRowBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_L + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_L + add_list[idx].nRowBit - 2, 1.0 / 2);
else if(add_list[idx].nRowBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_H + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_H + add_list[idx].nRowBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_8 + 1, 1.0/2);
}
}
else
{
FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_RAS, 1.0/4);
if(ErrorMark_L1 & 0x00FF0000)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS0, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+1, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_CASL, 1.0/8);
}
if(ErrorMark_L1 & 0xFF000000)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS1, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+2, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_CASH, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_0_8, 1.0 / 2);
}
}
}
if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 2)
if(count_bit32(ErrorMark_L1 & 0xFFFF0000) > 3)
{
NbErr++;
if((idxdraw == idx) && count_bit32(ErrorMark_L2 & 0x0000FFFF) > 6)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_WE, 1.0);
}
if(count_bit32(ErrorMarkBlank_L2 & 0x0000FFFF) < 3)
if(count_bit32(ErrorMarkOther_L1 & 0xFFFF0000) < 3)
{
if(add_list[idx].nColBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_2_0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0 + add_list[idx].nColBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0_Other + add_list[idx].nColBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_1_0 + add_list[idx].nColBit - 1, 1.0 / 2);
if(add_list[idx].nColBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_L + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_L + add_list[idx].nColBit - 2, 1.0 / 2);
else if(add_list[idx].nColBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_H + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_H + add_list[idx].nColBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_8 + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_8, 1.0 / 2);
}
if(add_list[idx].nRowBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_2_0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0 + add_list[idx].nRowBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_1_A0_Other + add_list[idx].nRowBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_1_0 + add_list[idx].nRowBit - 1, 1.0 / 2);
if(add_list[idx].nRowBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_L + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_L + add_list[idx].nRowBit - 2, 1.0 / 2);
else if(add_list[idx].nRowBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_H + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_H + add_list[idx].nRowBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_8 + 1, 1.0/2);
}
}
else
{
FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_RAS, 1.0/4);
if(ErrorMark_L2 & 0x000000FF)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS2, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+3, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_CASL, 1.0/8);
}
if(ErrorMark_L2 & 0x0000FF00)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS3, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+4, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_CASH, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_1_8, 1.0 / 2);
}
}
}
if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 2)
if(count_bit32(ErrorMark_L2 & 0x0000FFFF) > 3)
{
NbErr++;
if((idxdraw == idx) && count_bit32(ErrorMark_L2 & 0xFFFF0000) > 6)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexWE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, RES_WE, 1.0/4);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_WE, 1.0);
}
if(count_bit32(ErrorMarkBlank_L2 & 0xFFFF0000) < 3)
if(count_bit32(ErrorMarkOther_L2 & 0x0000FFFF) < 3)
{
if(add_list[idx].nColBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_3_0 + add_list[idx].nColBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0 + add_list[idx].nColBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0_Other + add_list[idx].nColBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_2_0 + add_list[idx].nColBit - 1, 1.0 / 2);
if(add_list[idx].nColBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_L + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_L + add_list[idx].nColBit - 2, 1.0 / 2);
else if(add_list[idx].nColBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_H + add_list[idx].nColBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_H + add_list[idx].nColBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_8 + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_8, 1.0 / 2);
}
if(add_list[idx].nRowBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_3_0 + add_list[idx].nRowBit, 1.0/1);
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0 + add_list[idx].nRowBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_2_A0_Other + add_list[idx].nRowBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_2_0 + add_list[idx].nRowBit - 1, 1.0 / 2);
if(add_list[idx].nRowBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_L + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_L + add_list[idx].nRowBit - 2, 1.0 / 2);
else if(add_list[idx].nRowBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_H + add_list[idx].nRowBit + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_H + add_list[idx].nRowBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_8 + 1, 1.0/2);
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_2_8, 1.0 / 2);
}
}
else
}
if(count_bit32(ErrorMark_L2 & 0xFFFF0000) > 3)
{
NbErr++;
if(count_bit32(ErrorMarkOther_L2 & 0xFFFF0000) < 3)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexRASCurrent, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, RES_RAS, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_RAS, 1.0/4);
if(ErrorMark_L2 & 0x00FF0000)
if(add_list[idx].nColBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS2, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+3, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_CASL, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0 + add_list[idx].nColBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0_Other + add_list[idx].nColBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_3_0 + add_list[idx].nColBit - 1, 1.0 / 2);
if(add_list[idx].nColBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_L + add_list[idx].nColBit - 2, 1.0 / 2);
else if(add_list[idx].nColBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_H + add_list[idx].nColBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_8, 1.0 / 2);
}
if(ErrorMark_L2 & 0xFF000000)
if(add_list[idx].nRowBit!=0)
{
FaultSource_addScore(pFaultSrcCtx, TMUTexCAS3, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, RES_CAS+4, 1.0/16);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_CASH, 1.0/8);
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0 + add_list[idx].nRowBit - 1, 1.0 / 1);
if(RamSizeMB>=2)
FaultSource_addScore(pFaultSrcCtx, MEMChip_3_A0_Other + add_list[idx].nRowBit - 1, 1.0 / 2);
FaultSource_addScore(pFaultSrcCtx, TMUTexADDR_3_0 + add_list[idx].nRowBit - 1, 1.0 / 2);
if(add_list[idx].nRowBit < 4)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_L + add_list[idx].nRowBit - 2, 1.0 / 2);
else if(add_list[idx].nRowBit < 8)
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_H + add_list[idx].nRowBit - 6, 1.0 / 2);
else
FaultSource_addScore(pFaultSrcCtx, RES_TEXADDR_3_8, 1.0 / 2);
}
}
}